What are the Avalon-MM addresses used for the JESD204 IP Core in dynamic reconfiguration for modifying the LMFSK and data rate parameters?

[SMcCa9]

Hello,

I am working on a project utilizing the JESD204B IP offered by Intel on an Arria V GZ FPGA using Quartus II Standard 14.0. Part of the project requires dynamic reconfiguration of the JESD204B link parameters, i.e. the LMFSK parameters and data rate configuration, for both transmit and receive. My understanding is that the JESD204 IP core allows reconfiguration through the Avalon-MM interface (with the right IP parameters selected in the IP itself) as stated in the JESD204B Intel FPGA IP User Guide. However, I am having trouble finding what addresses to write to in order to update the LMFSK parameters. What document should I refer to in order to find the memory mapping for the JESD204 IP core?

Thank you for your time,

Samual

[Nathan_R_Intel]

Hie Samual, My apologies for the delayed first response. I got your case mixed up with another JESD forum question; hence I missed providing an update. Firstly, for Arrua V GZ FPGA when using JESD 204B IP, you do not need to manually write to the registers to perform reconfiguration through AVMM. When a Trasceiver Reconfiguration Phy IP is connected to the JESD IP, a MIF file (configuration file) will be generated for every configuration. MIF file has all the register values required to perform reconfiguration. This details are explained in our JESD IP user guide (Section 1.6.4; Pg 54) below: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-design-ex-jesd204b.pdf The steps to perform reconfiguration through MIF file is also described in the Transceiver Phy User Guide: (Pg 17-43 to Pg17-46) https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf Please let me know if you need additional information on performing the reconfiguration for JESD204B IP. Regards, Nathan

[SMcCa9]

Hi Nathan,

Thank you for your response. I had gone through those PDFs before, but missed the details I was looking for.

I will look through the referenced materials and let you know if I have any follow up questions.

Best,

Samual

[Nathan_R_Intel]

Sure, let me know if you have follow up questions. Regards, Nathan

[SMcCa9]

Hello Nathan,

I do have a couple additional questions. I am trying to understand how the .MIF files are structured for reconfiguration. I should note that I have inherited the project I am working on, so I am still trying to understand the current project code before I modify it for an updated purpose. In the JESD204B IP Core Design Example User Guide Pgs. 59-60, the JESD .MIF format is referenced as follows:

Maximum Configuration MIF

WIDTH=16;

DEPTH=16;

ADDRESS_RADIX=UNS;

DATA_RADIX=BIN;

CONTENT BEGIN

0 : 0000000000000001; -- L (maximum config)

1 : 0000000000000001; -- M

2 : 0000000000000001; -- F

.

.

.

3 : 1111111111111111; -- End of MIF

[4..7] : 0000000000000000;

Downscale Configuration MIF

8 : 0000000000000000; -- L (downscale config)

9 : 0000000000000000; -- M

10 : 0000000000000001; -- F

.

.

.

11 : 1111111111111111; -- End of MIF

[12..15] : 0000000000000000;

END;

What I have done is search through my project directory for every .MIF file used in the design, and checked each file individually. What I found is that none of my files share the above format, or the PHY format for Arria V referenced on Pgs. 57-58. So my questions are such:

1. Does the JESD IP require a specific naming convention (or generate a .MIF file of a specific naming convention)?
2. Is this exact format required for the JESD .MIF file, or are other formats supported? If the later, where can I find information about the supported formats?

Since I didn't find a .MIF file for either of the referenced formats, and the JESD IP is certainly used in the design, I am a little confused.

Thanks again,

Samual

[Nathan_R_Intel]

Samual, Please check my replies to your questions below: 1. Does the JESD IP require a specific naming convention (or generate a .MIF file of a specific naming convention)? Answer: No specific naming convention is required. A mif file will be generated during Quartus fitter compilation. The mif file will have an extension of .mif. I just checked the JESD IP using Arria V GZ in Quartus II Standard 14.0 and it is able to generate a .mif file. However, please ensure you have instantiate the Transceiver Reconfiguration Controller from the IP Catalog and connect it to the JESD204B IP core through the reconfig_to_xcvr and reconfig_from_xcvr interface. Also check that you have enabled the following features in Transceiver Reconfiguration Controller: "Enable Channel/PLL reconfiguration" 2. Is this exact format required for the JESD .MIF file, or are other formats supported? If the later, where can I find information about the supported formats? Answer: Yes, this is the exact format required. Quartus is supposed to generate this file, hence follow my above guideline and you will be able to generate the .mif file. The information of MIF file format is documented in the user guide (PG 17-38): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf Regards, Nathan