I am working on a project utilizing the JESD204B IP offered by Intel on an Arria V GZ FPGA using Quartus II Standard 14.0. Part of the project requires dynamic reconfiguration of the JESD204B link parameters, i.e. the LMFSK parameters and data rate configuration, for both transmit and receive. My understanding is that the JESD204 IP core allows reconfiguration through the Avalon-MM interface (with the right IP parameters selected in the IP itself) as stated in the JESD204B Intel FPGA IP User Guide. However, I am having trouble finding what addresses to write to in order to update the LMFSK parameters. What document should I refer to in order to find the memory mapping for the JESD204 IP core?
Thank you for your time,
Thank you for your response. I had gone through those PDFs before, but missed the details I was looking for.
I will look through the referenced materials and let you know if I have any follow up questions.
I do have a couple additional questions. I am trying to understand how the .MIF files are structured for reconfiguration. I should note that I have inherited the project I am working on, so I am still trying to understand the current project code before I modify it for an updated purpose. In the JESD204B IP Core Design Example User Guide Pgs. 59-60, the JESD .MIF format is referenced as follows:
Maximum Configuration MIF
0 : 0000000000000001; -- L (maximum config)
1 : 0000000000000001; -- M
2 : 0000000000000001; -- F
3 : 1111111111111111; -- End of MIF
[4..7] : 0000000000000000;
Downscale Configuration MIF
8 : 0000000000000000; -- L (downscale config)
9 : 0000000000000000; -- M
10 : 0000000000000001; -- F
11 : 1111111111111111; -- End of MIF
[12..15] : 0000000000000000;
What I have done is search through my project directory for every .MIF file used in the design, and checked each file individually. What I found is that none of my files share the above format, or the PHY format for Arria V referenced on Pgs. 57-58. So my questions are such:
Since I didn't find a .MIF file for either of the referenced formats, and the JESD IP is certainly used in the design, I am a little confused.