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BIdro
New Contributor I
307 Views

What are the important settings for SDI-SD standard video communication? I use the IP-SDI-II up to SDI-HD and it works properly, but it does not work with SDI-SD. How can I generate a correct differential signal for SDI-SD standard?

The IP-SDI-II supports SDI-SD standard but It uses a 148.5 MHz clock signal as reference. It oversamples the data because the correct frequency should be 13.5 MHz. I use an interface component that expects a SDI-SD standard signal but I can't see a stable image in my monitor that supports SDI-SD standard. I see an image composed by multiple frames for an instant sometimes. I follow datasheet directives and the IP must generate a SDI-SD signal. 

Thanks for the help.

Bryan

 

 

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5 Replies
CheePin_C_Intel
Employee
102 Views

Hi Bryan,

 

As I understand it, you have some inquiries related to SD SDI with SDI II IP. Just would like to check with you which Quartus and device that you are using? Also, just wonder if you are using the SDI II IP as TX or RX?

BIdro
New Contributor I
102 Views

Hi Cpchan,

I'm using Quartus Prime 18.1 Standard Edition and the FPGA is Cyclone V - 5CGTFD5C5F2717.

I create a component with the wizard tool and I set it up to SD-SDI transmitter only.

I create an other component as SDI-SD receiver and I can see TRS,EAV, vertical and horizontal blanking signals from an external SDI-SD pattern generator with Signal Tap tool.

I connected TX_CLKOUT to TX_PCLK.

TX_CORECLK and XCVR_REFCLK are 148.5 MHz signals and they are generated using a PLL that has RX_CLKOUT (148.5 MHz) signal as reference frequency.

TX_DATAIN_VALID is connected to TX_DATAOUT_VALID that is sampled with TX_PCLK signal.

Is the TX set up properly?

thanks

Bryan

 

CheePin_C_Intel
Employee
102 Views

Hi Bryan,

 

Thanks for your update and explanation. I understand that you have a SDI RX and another SDI TX. You are feeding SD SDI video from external generator and when you observe with signaltap, the SDI RX seems to be working fine.

 

As I read through you description, just wonder if you are trying to perform a data re-transmit where you take the received data from RX, loopback to TX and transmit out to a monitor? If yes, as I understand it, generally you will need some FIFO in between to ensure correct data passing from RX to TX. Also, generally a VCXO is required to clean up the recovered clock before feeding into the TX as XCVR refclk.

 

You may try to generate an example design for Triple-Rate SDI II IP and then refer to the loopback FIFO in the example to see if it is helpful. You may also refer to the clocking connection for re-transmit application. For further details on the example design, you can refer to the "Design Example for Arria V, Cyclone V, and Stratix V Devices" section in the SDI II IP user guide.

 

Please let me know if there is any concern. Thank you.

BIdro
New Contributor I
102 Views

Hi Cpchan,

I used the fifo and the image is better but there are incorrect lines in each frame.

I saw with Signal Tap tool that, after some time, TX lost 1 read from fifo, so Luma and Croma are exchanged and I suppose that is the error.

My board has not an external VCXO to clean up the recovered clock before feeding into TX as XCVR refclk.

Is it wrong, if I use a internal PLL to generate tx-XCVR?

A VCXO has not a clock reference input but it has a voltage control input. How can I set the correct frequency for TX?

Can VCXO be connected to an internal PLL of mt FPGA (CYCLONE V GT)?

 

thanks

Bryan

CheePin_C_Intel
Employee
102 Views

Hi Bryan,

 

Sorry for the delay. I has been out for the past week. Regarding your latest inquiries, as I understand it, generally VCXO is required for clock cleaning before feeding into the TX as XCVR refclk. Yes, your understanding is correct, for VCXO, you would need to build your own logic to control the voltage input. You may further refer to your VCXO vendor on the controls required.

 

For your information, you may also try to refer to the following AN on example design for AV and SV which use VCXO. If I understand it correctly, the example design has some VCXO control logic which you may refer. However, please refer to your VCXO vendor for further details. The design also uses some loopback FIFO for re-transmit which you may refer to as well.

 

https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/an/an668.pdf

 

Note that I am unable to locate any CV example design for SDI II with external VCXO. Hopefully the AV and SV examples will be helpful.

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

 

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