I am trying to find out what the arbitration looks like when there are several masters accessing a single slave on an Avalon MM bus. I found some old information online (AN184) that describes this for SOPC builder and that there are arbitration assignments that can be set for each master slave pair. However I do not find any information about how this works or where I would set arbitration assignments in platform designer.
The only reference I found in the current Avalon Interface Specification is about a lock signal that is optional that will keep bus access to one master as long as it is not done with a burst access.
My specific platform designer example looks like this:
My specific questions are:
Any pointers to where this is documented or existing training or examples are greatly appreciated.
For question 1,3,4, you can refer to
For question 2,
If the master is starting a burst access indicated by the burstcount signal of more than 1, does the master keep access until the burst is done before the next master gets access?
Yes, basically, they should be waitrequest/valid when u assert the burst. you can refer to the link above page 101.