What happens if a signal value changes during the wait_request assertion?

[Mahdi]

Hello,

I have a question regarding the waitrequest signal in Avalon Memory-Mapped Interface.

In Avalon® Interface Specifications document, page 16, it is mentioned: "When waitrequest is asserted, host control signals to the waitrequest agent must remain constant."

My question is: what happens if I intentionally change the value of control signals at the end of the transfer? to be more specific, I need to de-assert the mem_en signal at the end of the transfer, and the value of this control signal comes from a register. As a result, when the waitrequest is asserted, the mem_en will have low value after one clock cycle. I don't like to have a combinational logic to de-assert the mem_en signal. That's why I use register. 

Is there any problem other than showing an error prompt in the Modelsim to change control signals after asserting waitrequest?

Thank you in advance. 

[sstrell]

Can you explain the use or design scenario here?  waitrequest is the input to a host (previously referred to as a master) in a Platform Designer system (typically) to tell it that an agent (previously referred to as a slave) is not ready to receive or process a read or write command, perhaps due to arbitration in the system interconnect or because the agent needs more time to respond to the command.  waitrequest can be controlled manually by an agent or automatically by the system interconnect.

It sounds like you are issuing a write command to an agent that has a register that outputs the mem_en signal you mention.  mem_en isn't part of the Avalon interface, so I presume you are controlling this agent which in turn controls mem_en.  Are you manually controlling waitrequest back to the host with this agent?

Is that an accurate description of what's going on here?  The value of mem_en should not be reliant on waitrequest.

[Mahdi]

Thanks for your answer. 

What I am doing is performing write transfer for let's say 1000 cycles. I designed my own IP core as the host, which is connected to the on-chip memory with AV_MM interface. mem_en signal is connected to write signal which indicates a valid write transfer. My question is if in the last transfer (1000th write), when waitrequest goes high, the host drives 0 on mem_en (or write signal) afterward, would be any problem? Let's say the mem_en signal was 1 during entire write transfers (for 1000 cycles). I know that agent expects a constant value for all control signals during the time that waitrequest is asserted. But, since this is the last transfer and there would not be any other transfer, would be any problem if I change the control signals (here mem_en or even address) when waitrequest is 1? 

[sstrell]

OK, that clears it up a little bit.  I didn't realize mem_en was your write signal from the host.  To answer your question, if the 1000th write has completed (host asserted control signals and waitrequest was low for 1 cycle), then you can do whatever you want.  But it sounds like you're saying that waitrequest goes high on that last write, in which case, the last write has not completed yet and the interconnect is telling the host to wait before performing that final write.

Again, I'm not sure I'm interpreting your situation correctly.

[Mahdi]

Sorry. I should've been more clear.
I was trying to say that after last write, since there is no other write, the mem_en goes down, but this happens exactly when the waitrequest is asserted. That wouldn't have any effect on write transfer, but still I get error in Modelsim saying that control signnals shouldn't change during the time waitrequest is high. So, I just want to make sure there is no problem in the design. It's just a safe error.

Again, thanks for your answers.

[sstrell · Accepted solution]

As long as all your writes completed successfully, that should be OK.  Is it a BFM in your simulation saying there is an error?

The interconnect may, at that point, be asserting waitrequest for something else happening in the system.  Your host doesn't care anymore because it's done with its transfers.