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What multiplier can do 16 bit by 26 bit?

Honored Contributor II



I am new to Altera. I read an article on division with APEX, which was an old device. It said: 


On an Altera APEX device, when combining the LUT and multiplier into a single division module, a 16 bit by 26 bit multiplier consumes 838 logic elements (LEs), operating at 25 MHz clock frequency and total memory consumption of 53248 memory bits for the specific target FPGA device 



I know modern FPGA has 18X18 multipliers. The above statements look like a memory lookup table multiplier? How to implement it in new FPGA?  


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Honored Contributor II

Im not sure what the question is. You would implement it that same way as the apex if you wanted a memory multiplier. But now its easiest just to do the multiply in hdl and let the compiler infer the hardware.