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Altera_Forum
Honored Contributor I
1,109 Views

What rounding conventions in Arria 10 floating point DSP blocks?

I'm looking for the rounding method(s) used in the hard DSP blocks in floating point modes in the Arria 10. In particular, I am using the sp_mult-add and the sp_vector2 modes. I have not been able to manipulate my matlab model to match the rounding produced by the twentynm_fp_mac simulation model (which is encrypted, so I can't look under the hood either). I'm not sure of the internal bit widths, or whether rounds are performed at the denormalize into the adds or not, and if so is it ieee 754 default round to nearest, round to +/- infinity, round to zero or truncation? Is extra precision carried between the multiplier and the adder (i.e. fused operation)? If so, how many bits and is it rounded? Unfortunately the customer insists the hardware be a bit true match to the matlab model as a condition of acceptance. Hopefully someone here can enlighten me and save me a lot of hours of reverse-engineering the sim model to divine the correct rounding model.

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Altera_Forum
Honored Contributor I
35 Views

In case of doubt, I would expect that the Arria 10 Native Floating-Point DSP supports the same rounding mode as standard FP IP, see user guide.

Altera_Forum
Honored Contributor I
35 Views

Hi,  

 

The rounding method in the Floating point hard block is round-to-nearest-event.  

 

Best Regards, 

Terence 

 

(This message was posted on behalf of Intel Corporation)
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