What's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus?

[JBayl]

My setup is:

• Cyclone 10 GX Development Board
• FPGA Design contains the Generic Serial Flash IP, PCIe hard ip, and the JTAG to Avalon Master.
• Testing this setup through System Console

I was able to verify that the read flash ID and read flash memory works. Page Program doesn't work. Some sequences causes the system to hang and the only way to recover is a reboot.

The page program script I'm using works when i remove the PCIe Hard IP core from the design. So, its just the Generic Serial Flash IP and the JTAG to Avalon Master.

Thanks!

[JohnT_Intel]

Hi,

I would recommend you to only connect it to single Avalon-MM master to the Generic Serial Flash IP. May I know if there is any issue if you are connecting only to the PCIe hard IP?

[JBayl]

Hi JohnT,

Issue is the same when we try accessing the flash device through software through PCIe (no JTAG Master). We can read the flash ID and what we think is flash memory but we can't write to it. This basically led us to debug the IP via JTAG Master then find that page write also doesn't work whenever PCIe hard IP is present. Suggestions?

r/joel

[JohnT_Intel]

Hi,

May I know if you are able to send me your Quartus design? I am suspecting that the issue is due to the timing constraint.

[JBayl]

Hi JohnT,

Yes I can send a QAR file. I don't see an option to attach file here... email?

Thanks!

[JohnT_Intel]

Hi,

You should be able to observed attach symbol when you are are replying the forum or you can sent it through private message.

[JBayl]

Direct message sent. Thanks!

[JohnT_Intel]

Hi,

I have try to modify the file and compile in Quartus 20.1. This design only have PCIe to Generic Serial Flash Interface. Please try to see if you are still observing any issue.

If yes, please provide me the step you used to send the data through PCIe.

[JBayl]

Hi John,

I have forwarded the JIC to SW. What have you done and can you forward your QAR so I can study and compare while I wait for SW to evaluate your JIC?

Thanks!

[JohnT_Intel]

Hi,

I just remove the JTAG Master IP and observed the timing analysis. Nothing much changes.

[JBayl]

Hi John,

Here's our code:

// NEW for testing Config SPI Flash FPGA IP core

#define REG_FLASH_IP_CSR 0x10000000 // offset from PCIe BAR2 base address

// the following are offsets from REG_FLASH_IP_CSR

#define FLASH_CONTROL_REG 0x00 // Control register bit8 1=4byte add,keep bit0 at 1, 0 = disable outputs

#define FLASH_OP_PROTO_SET 0x10 // Operating Protocol Setting Register

#define FLASH_RD_INST_REG 0x14 // Read Instruction Register

#define FLASH_WR_INST_REG 0x18 // Write Instruction Register

#define FLASH_CMD_SET    0x1C //31-21 reserved|20-16 #dummy cycles|15-12 #w/r data bytes|11 0=wr 1=rd|10-8 #address bytes|7-0 opcode|

#define FLASH_CMD_START  0x20 //write 1 to start

#define FLASH_ADDRESS    0x24 // address for the operation

#define FLASH_WR_DATA0   0x28 // first 4 bytes write data

#define FLASH_WR_DATA1   0x2C // last 4 bytes write data

#define FLASH_RD_DATA0   0x30 // first 4 bytes read data

#define FLASH_RD_DATA1   0x34 // last 4 bytes read data

#define FLASH_IP_MEM     0x8000000

#define FPGA_ONCHIP_MEM 0x100000

void PCIJTAG2_API FlashIpStuff(void)

{

 U32 DataRead;

  WritePciJtag(REG_FLASH_IP_CSR+FLASH_OP_PROTO_SET,0x0); // normal extended mode for all operations

  // Read Device IDs

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x000489F); // opcode 9F, no address, write bit 11 set = read, 4 bytes, 0 dummy cycles

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

 DataRead = ReadPciJtag(REG_FLASH_IP_CSR+FLASH_RD_DATA0);

 printf("\nDeviceID = 0x%x\n",DataRead);

  // Clear sector protect by writing the status Register

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x00001001); // opcode 01, write bit 0 = write

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_WR_DATA0, 0x20); // bit 5 for bottom start - all protect bits cleared

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

// Enter 4 byte addressing 

  FlashSetWriteEnable();

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x000000B7); // write opcode b7 - no address or data bytes

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CONTROL_REG,0x00000101); // Tell Flash IP we are using 4-byte addressing

  FlashEraseSector(0xB000000); // sector 11 64KB sectors

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_WR_INST_REG,0x00007012); // 70h status read, 12h 4-byte page program opcode

 WritePciJtag(FLASH_IP_MEM+0xB00000,0xFACEFACE);

  CheckStatus();

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_RD_INST_REG,0x00000013); // 0 dummy cycles 13h 4-byte read opcode

 DataRead = ReadPciJtag(FLASH_IP_MEM+0xB00000);

 printf("\nDataRead = 0x%x\n",DataRead);

}

void FlashSetWriteEnable(void)

{

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET, 0x00000006);// write opcode 6

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

}

void FlashEraseSector(U32 address)

{

// Erase using 4 byte address

 FlashSetWriteEnable();

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x000004D8); // write opcode D8 sector erase - 4 address bytes

  WritePciJtag(REG_FLASH_IP_CSR+FLASH_ADDRESS,address); // address

 WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

}

void CheckStatus(void)

{

 U32 DataRead,i=0;

 do

 {

   Sleep(5);

   WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x0004870);//status read of 4 bytes of data

   WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

   DataRead = ReadPciJtag(REG_FLASH_IP_CSR+FLASH_RD_DATA0);

 }while((DataRead != 0x81818181)&& (i < 500));

}

Output:

DeviceID = 0x1021bb20

DataRead = 0xffffffff

[JohnT_Intel]

Hi,

Thanks for providing the code but what I observed is the code for each procedure.

May I know which procedure do you run? May I know if you are running the same procedure when you used JTAG Master? Are you able to use SignalTap to see if the command is send correctly into the Generic Serial Flash Interface IP?

[JBayl]

Hi,

The procedure that was run is PCIJTAG2_API FlashIpStuff. It's the same sequence used on System Console using TCL script. We didn't try using SignalTap because the same sequence is being executed on TCL and SW and all works on both except for Page Program on SW. The Avalon bus is assumed to be OK since we can read the flash ID and read from the flash device. The IP handles the EPCQL interface, so what part should we use SignalTap on?

[JohnT_Intel]

Hi,

I bbserved that you are using standard SPI protocol which the command, address and data is used for standard and not extended mode.

"WritePciJtag(REG_FLASH_IP_CSR+FLASH_OP_PROTO_SET,0x0); // normal extended mode for all operations"

For extended SPI mode, you will need to set it to

"WritePciJtag(REG_FLASH_IP_CSR+FLASH_OP_PROTO_SET,0x22220); // normal extended mode for all operations"

Please be aware that this setting is not suitable for sector erase but only for read and write operation that you plan to use extended SPI mode.

The write instruction that you are using is for extended SPI mode.

"WritePciJtag(REG_FLASH_IP_CSR+FLASH_WR_INST_REG,0x00007012); // 70h status read, 12h 4-byte page program opcode"

So you will need to make the changes so that you are running the write correctly to opcode 02h if you would like to use normal SPI mode.

Opcode 13h to performed read. May I know if you are able to use 03h opcode to performed read?

WritePciJtag(REG_FLASH_IP_CSR+FLASH_RD_INST_REG,0x00000013); // 0 dummy cycles 13h 4-byte read opcode

If you plan to use extended SPI mode then you will need to use Opcode EBh,

[JohnT_Intel]

Hi,

Have you try the solution that I provided?

[JohnT_Intel]

Hi,

Have you tried to modify the GSFI setting?

[JohnT_Intel]

Hi,

Have you tried to modify the GSFI setting?