FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5917 Discussions

What will happen if I generated a FIFO using the IP but I tied the ACLR and SCLR to '0' (i.e. I don't have a ALCT or SCLR signal input) ?? Will it still work??

MKwan
Beginner
521 Views
 
0 Kudos
1 Reply
AnandRaj_S_Intel
Employee
117 Views

Hi @MKwan​ ,

 

Yes, Because ACLR and SCLR are optional ports.

If we don't use ALCT or SCLR input, FIFO will work fine.

 

Refer table:2 from below link

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fifo.pdf

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Regards

Anand

Reply