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Honored Contributor I
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What would be a good architecuture

Hello 

 

I've designed a IP in verilog which is defined by the following port list: 

 

module supvervisor ( 

input wire in_clk, 

input wire in_nReset, 

input wire in_enable, 

 

input wire [15:0] in_bitTime, 

input wire [15:0] in_bitTimeVicinity, 

input wire [31:0] in_bitTimePattern, 

input wire [31:0] in_bitTimePatternCont, 

 

input wire [31:0] in_cycleTime, 

input wire [31:0] in_cycleTimeVicinity, 

 

input wire [31:0] in_signalTime, 

 

output reg [31:0] out_errReg, 

output reg [31:0] out_statReg, 

); 

 

The module manly consists of a finite state machine and monitors a RS485-Line. I can simulate the module and it seems to work properly. 

 

The complete design must monitor not only one RS485-Line but also 24 lines in parallel and must be connected by avalon to NIOS. All module inputs can be connected parallel. The module outputs must be seperated for each of the 24 modules. 

 

So my question: What would be a good way to connect the complete design to NIOS? I can think of the following ways: 

 

1) Each single module is treated as Memory Mapped Slave and can be instanciate 24 times in the SOPC Builder. For test pupose I've done this. The problem is that it almost won't fit into my CIII (98%). 

 

2) Designing a top module which connects all the inputs of the 24 modules together and uses a big MUX for reading each of the outputs. This top module is connected through Memory Mapped Slave to avalon. Almost the same behavouir linke in 1). 

 

3) I've heard and read using a DPRAM could be an alternative. But I don't know how to do this, i.e. I can't see the advantage in reducing LEs and LABs. Has anybody an example of this architectrue? 

 

Thank you 

 

brunjak
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