Where to download XCVR IP Core for Cyclone 10 GX and updated design example?

[KRoma6]

I am using the Cyclone 10 GX to test the Transceivers with the help of the design example. The version of Quartus Prime was stated as 17.1.1. I downloaded the base 17.1 version and installed the update file which automatically put it at 17.1.2. When installing the reference design into my project, it is saying it is not compatible with the version of Quartus prime I am using. I when forward with attempting to compile the IP but it came back with this error:

Error: Missing file G:/Programs/QuartusPrimeV17v1/nios2eds/hw_library.iipx

Error: Missing file G:/Programs/QuartusPrimeV17v1/nios2eds/sw_library.iipx

Do I really have to find the exact 17.1.1 version of Quartus Prime or is there an updated design example? Can I fix this by finding the correct libraries?

Thanks,

-Kyle

[CheePin_C_Intel]

Hi,

As I understand it, you have some inquiries related to an example design. To ensure we are on the same page, would you mind to further elaborate on which specific example design that you are referring to? It would be great if you can share with me the download link or weblink to the design as well.

Based on my understanding, generally an example design (not IP generated) is created and validated based on specific Quartus version. To ensure compatibility, it is recommended to use the same version to work with it.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[KRoma6]

Hi,

You are correct. I realize the XCVR IP Transceiver PHY is available in the Platform Designer library but I am using a design example tailored for the Cyclone 10 GX Dev Board.

Here is the link:

https://fpgacloud.intel.com/devstore/platform/17.1.1/Pro/cyclone-10-gx-xcvr-toolkit-reference-design/

I am using the 17.1.2 version off Quartus, do I really need to downgrade to the 17.1.1 version for this to work?

I am leverage off this design to do some testing on the Dev board but I am running into the <sw_library.iipx> and <hw_library.iipx> issues.

Thanks,

-Kyle

[CheePin_C_Intel]

Hi,

Thanks for your update and reference to the design in the Design Store. I am not sure what might be wrong when you use Q17.1.2 which lead to the issue that you are observing. However, to workaround this to allow you to proceed, I would like to suggest the following:

1. You can create a simple test design in RTL with ATX PLL + Reset controller + Native PHY

i. You may refer to the example design for the IP configuration

2. In the Native PHY, turn on the following in Dynamic Reconfiguration tab:

i. Enable dynamic reconfiguration

ii. Enable Altera Debug Master Endpoint

iii. On all the options under Optional Reconfiguration Logic

3. Connect the pinout following the example design

4. Create SDC for the top level design

5. After compilation and programming the design, you may try to use Toolkit to interface with the design.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin