In my design targeting a Cyclone IV E FPGA I use several dcfifo FIFOs. I observed that the first write/read FIFO transaction (after the FPGA is configured) sometimes fails in hardware. In such an error case, the output signals of the FIFO (i.e. q, empty, usedw etc.) behave completely unexpected; see the attached signaltap plot. For instance, the FIFOs fill level wrusedw jumps from 0x00 to 0x3F after the first write transaction.
Hi Shyan ,
Thanks for looking at it,
I found this kdb.
It seems that additional constrain need to be added. As I do not have a design to test out, could you try to add this in manually per kdb written?
Or, could you share your design so I can duplicate the issue?
I followed the guidance described in the kdb link. Unfortunately, the issue is still there.
However, I found workaround that seems to work: When adding the aclr port of the FIFO and resetting the FIFO at start-up the issue could not be observed anymore.
It seems that the aclr port is needed, altough the data sheet does not state that (the aclr port is optional).