FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

Why does the Clipper MegaCore Function have limitations on minimum frame width and height?

RSher11
Beginner
233 Views

Why does the Clipper MegaCore Function have limitations on minimum frame width and height? Minimum image width is equal to 32 pixel. Minimum image height has the same limitation.

0 Kudos
2 Replies
Vivek_G_Intel
Employee
185 Views

The original Avalon-ST Video protocol mandates 32x32 as the minimum frame size. This limit feels arbitrary but there is actually a technical reason for it. The first round of video IP was built with a HLS compiler that wouldn't pipeline loops if they did not have a minimum number of iterations.

RSher11
Beginner
185 Views
Reply