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Valued Contributor III
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Why my ddr2 ip don't work in fpga ep4cgx22cf19c8 ?

I download ddr2(micro ddr2 chip mt47h64m16hr) ip core to fpga EP4CGX22CF19C8 and latch the ddr2 pin in bank 3 and bank4 

then i caputure the signal local_wdata local_read local_read_req local_write_req and so on by signatap but all the signal 

in signaltap doesn't change and keep in on the reset_n state WHY DDR2 IP DOWNLOAD TO FPGA IT DON'T WORK? 

my opration as :  

1): I generate the ddr2 ip by the MegaWizard Plu-In Magager of quartusII 10.1 

2): I download the ddr2 ip core contain :ddr2_example_driver and ddr2_example_top block which are generated by MegaWizard Plu-In Magager and simulation ok in simulation modelsim se 6.6c 

3): I compile the ddr2 ip core without -slack path : timing nor probem 

4): I attach the ddr2 ip core pin in bank2,and bank3 with FPGA data sheet . 

5): I generate the ddr2 ip core for FPGA : EP3C25F324C8 and download to fpga and caputure the signal by signaltap THE IP CORE WORK CORRECT; 

THEN I KEEP THE IP SET AND GENERATE DDR2 IP CORE FOR EP4CGX22CF19C8 AND DOWNLOAD BUT THE SIGNALTAP DOSEN'T CATPTURE THE SIGNAL CHANGDE WHY?? 

6): my EP4CGX22CF19C8 fpga in pcb board just connect with ddr2 chip ,osc_clock and power ;it work ok with counter ip pcb is ok. 

WHY MY DDR2 IP DON'T WORK IN FPGA EP4CGX22CF19C8 ?
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Valued Contributor III
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--- Quote Start ---  

I download ddr2(micro ddr2 chip mt47h64m16hr) ip core to fpga EP4CGX22CF19C8 and latch the ddr2 pin in bank 3 and bank4 

then i caputure the signal local_wdata local_read local_read_req local_write_req and so on by signatap but all the signal 

in signaltap doesn't change and keep in on the reset_n state WHY DDR2 IP DOWNLOAD TO FPGA IT DON'T WORK? 

my opration as :  

1): I generate the ddr2 ip by the MegaWizard Plu-In Magager of quartusII 10.1 

2): I download the ddr2 ip core contain :ddr2_example_driver and ddr2_example_top block which are generated by MegaWizard Plu-In Magager and simulation ok in simulation modelsim se 6.6c 

3): I compile the ddr2 ip core without -slack path : timing nor probem 

4): I attach the ddr2 ip core pin in bank2,and bank3 with FPGA data sheet . 

5): I generate the ddr2 ip core for FPGA : EP3C25F324C8 and download to fpga and caputure the signal by signaltap THE IP CORE WORK CORRECT; 

THEN I KEEP THE IP SET AND GENERATE DDR2 IP CORE FOR EP4CGX22CF19C8 AND DOWNLOAD BUT THE SIGNALTAP DOSEN'T CATPTURE THE SIGNAL CHANGDE WHY?? 

6): my EP4CGX22CF19C8 fpga in pcb board just connect with ddr2 chip ,osc_clock and power ;it work ok with counter ip pcb is ok. 

WHY MY DDR2 IP DON'T WORK IN FPGA EP4CGX22CF19C8 ? 

--- Quote End ---  

 

 

 

Close the project, then delete both the DB and Increment_db directories. The try it again. 

 

Some wierd stuff gets in there and you need to clean it out.
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