With the DDR4 EMIF interface running at >1000MHz, do we need to use board traces to deskew the package delays or is Quartus able to take care of this deskewing for us?

[RTang1]

We are designing a board that uses an A10GX027 with a DDR4 interface running at 1000MHz.

In section 5.4.5, it states that if we do not enable the package deskew option, Quartus Prime will adjust the skews on the appropriate signals and that we don't need to adjust for the delays with board traces.

In section 5.4.5.3 if we plan to use the DDR4 protocol above 933MHz, we must perform package deskew. Does this mean we must perform deskew with board traces (i.e. enable "Package deskewed with board layout" in EMIF board parameters)? Or does it mean we must deskew with either board traces OR by allowing Quartus Prime to deskew?

This boils down to one question:

With the DDR4 EMIF interface running at >1000MHz, do we need to use board traces to deskew the package delays or is Quartus able to take care of this deskewing for us?

[sstrell]

The answer depends on your board. Is your board designed (or will be designed) to take into account the package delays? If your board will take these delays into account, turn on the "Package deskewed with board layout" options and look in the .pin file after compilation to see what the package delay values are. Then incorporate these into your board design.

If you want calibration to handle this instead of adjusting your board design, turn the deskew options off. However, as you note from the documentation, for DDR4 at that speed, it is recommended to deskew in your board design, so the deskew options should be turned on. You shouldn't rely on the calibration to be able to account for the skew at that speed.