FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

XAUI Tx lane reversal

Honored Contributor II

Hi everyone, 

I designed a board with Arria V GX on it. 

I have mistakenly reversed (In relation to Rx) the XAUI Tx lanes on my new board. 

The compilation fails for the current pin layout. 

When I reverse the Tx lanes, compilation succeeds, as expected. 

I noticed in "Altera Transceiver PHY IP Core User Guide" 7-13 that: 

xgmii_tx_dc[71:0] contains 4 lanes of data and control for xgmii. each lane 

consists of 16 bits of data and 2 bits of control. 

• lane 0–[7:0]/[8], [43:36]/[44] 

• lane 1–[16:9]/[17], [52:45]/[53] 

• lane 2–[25:18]/[26], [61:54]/[62] 

• lane 3–[34:27]/[35],[70:63]/[71] 



My question is: Can I use the above mentioned fact to reverse the lanes in the xgmii_tx_dc bus and compensate for the serial Tx lanes? 

Will it affect the link fault mechanism? 




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3 Replies
Honored Contributor II



Have you tried the assignment? You can find this in the Transceiver PHY IP User Guide. 


Example 7-1 shows how to remove the restriction on logical lane 0 channel assignment in Stratix V 

devices by redefining the pma_bonding_master parameter using the Quartus II Assignment Editor. In 

this example, the pma_bonding_master was originally assigned to physical channel 1. (The original 

assignment could also have been to physical channel 4.) The to parameter reassigns the 

pma_bonding_master to the XAUI instance name shown in quotation marks. You must substitute the 

instance name from your design for the instance name shown in quotation marks 

Example 7-1: Overriding Logical Lane 0 Channel Assignment Restrictions in Stratix V Devices 

set_parameter -name pma_bonding_master "\"1\"" -to "<xaui 

instance name>|sv_xcvr_xaui:alt_xaui_phy|sv_xcvr_low_latency_phy_nr: 




Swapping parallel data bus wouldn't work because the XAUI PHY IP expects start-of-packet symbols come to Lane 0.
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Honored Contributor II

Hi kkaibara, 

Thanks for your reply. 


I have tried overriding logical lane 0 channel assignment restrictions. It works only for a duplex reverse swap. My swap is from a simplex point of view (only tx). 


Simulating "altera_eth_10g_mac_xaui design example": 

On the top level "tb.sv" I reversed xaui_tx_data in this manner: 

xaui_rx_data[3] = xaui_tx_data[0] 

xaui_rx_data[2] = xaui_tx_data[1] 

xaui_rx_data[1] = xaui_tx_data[2] 

xaui_rx_data[0] = xaui_tx_data[3] 


When I tried swapping lanes in xgmii_tx_dc[71:0], I succeeded in overriding the "local fault" generation and I received the start-of-packet on xgmii_rx_dc[71:0]. The problem is with the last TXD and TXC of each frame. 



TX before lane reversal: 

TXC[7:0] c0 

TXD[63:0] 07 FD FA 88 f5 DC D7 D6 


TX after lane reversal: 

TXC[7:0] 30 

TXD[63:0] 88 FA FD 07 D6 D7 DC f5 



RXC[7:0] c8 

RXD[63:0] fe FD FA 88 fe DC D7 D6 


Can you understand what generates the 0xFE? 



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Honored Contributor II

Hi Dror, 


The XAUI PHY is not a simple Parallel to/from Serial converter. The PHY checks the incoming data stream to ensure that the character code transition follows IEEE802.3 Clause 48 state diagram. For example, Termination code (data=0xFD, ctrl=0x1) must be followed by Idle code (data=0x07, ctrl=0x1), otherwise the XAUI PHY IP recognizes the code transition is invalid. In your case, Idle is followed by Terminaiton, that is invalid, and then the PHY IP injected Error code (data=0xFE, ctrl=0x1) as an error flag. 


If simplex swap is not allowed, the board has to be re-designed unfortunately.
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