Now I use HPC ii to operate two ddr2 chip(parallel connet to the FPGA,act as a 32 bit data bus ddr2),and the operate mode is full rate,
and I have 10 input ports to write to and 10 output ports to read from the 32 bit ddr2, each time I will write 64bit*8 datas to or read 64bit*8 datas from ddr2, but I have notice when I simulate the HPC II,that after I assert the local_read_req and local_burst signal ,almost delay about 30 phy_clk,and then the HPC II assert the local_rdata_valid,in the 30 phy_clk,can I do something?
Can I do operate the HPC II to write to or read from the DDR2 in the 30 phy_clk delay ???
In the situation switching to write 64bit*8 datas to or read 64bit*8 datas from the DDR2 via the hpcii with full mode each time, how much value of effiency the HPC II will be?? Wil the 30 phy_clk delay influence the effiency ?
http://www.alteraforum.com/forum/attachment.php?attachmentid=10329&stc=1
