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about CAS latency setting in ddr_hp_controller v.9.1

Altera_Forum
Honored Contributor II
819 Views

Hi, 

 

I have tried to generate full rate ddr_hp_controllerv.9.1 with clock frequency of 128mhz in stratixIII device. I noticed that Altera only support CL=3 for stratix III device. But the ddr data sheet provided by Micron and Samsung state that the frequency for CL=3 have to be in the range of 133mhz to 200 mhz. I hope someone can help to answer following questions : 

 

1. I am wondering why Altera hpc and hpcII do not support CL=2.5 or CL=2 in strxIII? CL =2 or 2.5 will allow using lower frequency according to ddr data sheet. 

 

2.My understand of CAS latency is just a number of clock cycle waiting from CAS stroke to read data shown up on memory bus. If I use the Altera hp_contoller with CL=3 and a lower than spec. frequency, such as 128mhz, to interface Micron DDR, what bad things could happen? 

 

 

3. Any way around so that I can still use Altera DDR HPC or DDR HPCII but with f=128mhz? 

 

Thank you in advance.
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1 Reply
Altera_Forum
Honored Contributor II
111 Views

Hi, 

 

I have not worked with DDR, but I have worked with DDR2. My understanding is that the MAXIMUM frequency is limited by the CAS latency while the MINIMUM frequency is not influenced by CAS latency. The minimum frequency is determined by the DLL (not sure if DDR has DLL?). Therefore you can run your memory at 128MHz with a CL=3 if the memory device is specified to be able to run at 128MHz. Maybe at 128MHz you could have used CL=2.5 or CL=2, but if the core does not support it, you will have to live with a CL=3. 

 

Regards, 

Niki
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