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Valued Contributor III
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aclr and sclr - difference

Hi, 

 

can someone please explain me why some DSP builder blocks have aclr and others sclr input ? what's the difference and how does it influence the generated vhdl code ? 

 

Thanks ppl !
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Valued Contributor III
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aclr = asynchronous clear. Registers are reset immediatly. 

sclr = synchronous clear. Registered are reset on the next rising edge of the clock. 

 

using aclr can be dangerous if you dont control it properly. If you have to use aclr ports, its best to reset them from a synchronous source. Aclr can be useful in VHDL code for setting powerup values 

 

sclr is much safer (and recommended) but you cannot infer power up values from it.
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Valued Contributor III
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Ok thanks, so I can use the same synchronous reset signal for aclr and sclr ports without any problems, right ?  

 

In respect to the DSP Altera Blocks, the "sclr" is always positive flank reset (0->1), and what about aclr ? Is it negative or positive ?  

 

Regards, 

Joel
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Valued Contributor III
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Yes you should be able to - but remember that because aclr is immediate, the blocks with sclr will come out of reset 1 clock cycle later than the ones with aclr. 

 

Aclr should follow the same rules. Internal logic is usually best kept as active high for ease of reading. Active high or low uses the same amount of current, unlike on inter-device connections on a PCB, that are usually active low, to reduce current draw.
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Valued Contributor III
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Thanx, I'm not quite sure about the aclr though. I'm using the Clock Block (DSP Builder , Altera Blockset) where the aclr can be set to active low/high. So, I suppose that the logic of others Blocks will be adjusted to the setting from Clock Block accordingly. Can you confirm it ?  

 

Also, to confuse me even more, there is a Global Reset Block ,called SCLR, described as follows 'Any signal driven by global reset gets connected to the asynchronous global reset circuitry'. If its asynchronous, why is it called SCLR then ? :) 

 

Best Regards, 

Joel
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Valued Contributor III
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read about setup and hold, and metastability.

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Valued Contributor III
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--- Quote Start ---  

read about setup and hold, and metastability. 

--- Quote End ---  

 

 

thank you, that was the answer I was looking for ... omg what a nerd
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Valued Contributor III
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Assuming that reply was not cynical (I was trying to answer your question exactly as you asked it...) 

 

Note that sclr signals generate muxes on the data input of flipflops. Thats how (or one way) the clear is made synchronous.  

 

aclr works more directly internal to the Flip-Flop ...read up about J-K and RS flip flops to understand more about their internal workings. 

 

Also note that aclr signals tend to become global nets whereas sclr signals do not have to be. Global signals are a a precious resource. 

 

I would suggest that if you have an external reset signal or even a power up reset signal ... have this signal logically ANDed with the lock output of the clock being used and pass this through at least two flip-flops. Assign the signal on the output of the last flip-flop to be global and use this as your aclr in the design. Lots of reasons related to the previously mentioned digital synchronous design requirements of setup, and hold for this. 

 

Lastly ... dont forget that typical statemachines are also synchronous processes... easy to forget that. The first state can become an asynchronous state if poorly designed...and this can lead to violations of setup and holds on signals that transition when leaving this state. Be carteful with statemachines. If you resync the aclr global as previously mentioned you will be fine. 

 

I hope this helps. Good luck
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Valued Contributor III
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I can not agree more with you. However, you do not answer my questions. This is DSP Builder Forum, therefore my questions are related to the DSP Builder Altera Blockset.  

I was previously asking about a block called 'Clock Block' where one can set the aclr reset flank to active low/high. The question was, whether this setting has an influence on aclr input of other blocks. The second question was related to a block called ' Global Reset Block'.  

 

To be even more clear I say it once more - I DO NOT have any problems with setup/hold/metastability violations. I was asking about DSP Builder Blockset behaviour bacause I was to lazy to check the generated vhdl files. 

 

I hope this is clear now,  

best regards
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Valued Contributor III
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Setting the clock block's reset to active low means that the input reset to the DSP Builder system is expected to be low. DSP Builder will convert that reset to whatever is expected by its own internal blocks.

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