FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5885 Discussions

alt_avalon_sgdma_do_async_transfer() :

Altera_Forum
Honored Contributor II
820 Views

Hi All , 

What would be the offset of descriptor_base – base address of the dispatcher descriptor slave port ? 

The offset of this address goes undocumented in REGISTER MAP section of ug_embedded_ip.pdf chap 25 or i may be missing it ?? 

 

 

Thanks, 

John
0 Kudos
0 Replies
Reply