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alt2gxb: pll_locked keeps low

Altera_Forum
Honored Contributor I
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basic mode 

refclk 50M diven by input pin 

primary data rate:1000M 

serial loopback. 

reset flow: gxb_powerdown->when pll_locked->deassert tx_digitalreset and rx_analogreset..... 

the project can work well last week either in loopback mode or not. 

but today, the serdes can not work, I found the reason is that trasmitter PLL can not lock, the pll_locked signal keeps low. 

is it a Quartus's IP bug? 9.1 sp1:confused: 

regards.
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