Honored Contributor I
08-31-2011 11:53 AM
basic moderefclk 50M diven by input pin primary data rate:1000M serial loopback. reset flow: gxb_powerdown->when pll_locked->deassert tx_digitalreset and rx_analogreset..... the project can work well last week either in loopback mode or not. but today, the serdes can not work, I found the reason is that trasmitter PLL can not lock, the pll_locked signal keeps low. is it a Quartus's IP bug? 9.1 sp1:confused: regards.