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altera TSE compiled in fpga VHO

Honored Contributor II

Hi to all. 

I use cyclone4 and i make a project that use the tse (triple speed ethernet) megafuncion. 

It compiles without errors. 

Now i have a vho (vhdl output) for the simulation. 


If i use this vho and the right libs i can simulate my project with modelsim. 

The simulation is ok for my circuits, except for the tse module. 

The project must send out tx packets on the ethernet tse. 

I make a fsm that drives the avalon streaming signals (sop, eop, etc) and a fsm that initializes the reg 0x02 with data 0x00000001 of the tse. 

The reg 0x01 bit0 is tx enable. 

But the data of MII tx stays at 0x0 always. 

Which is the correct sequence to initialize the module tse? 

The simulation does in this way it work?
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Honored Contributor II


my fsm had a bug. 

Now i can simulate my FPGA project with TSE inside. 

Best regards!
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