i’m trying to run the a10_soc_devkit_sgmii (arria 10) project (https://rocketboards.org/foswiki/Documentation/GSRD181ReleaseNotes#Release_Contents 1) with some modifications.
I’m running into some timing issues that seem to be from the altera_gmii_to_sgmii ip.
attached is a screenshot from the report and the project archive.
You will also need to take a look at:
page 183 although this is A10, It should be apply to all device.
Basically, it mention that you need a different IO standards if your frequencies running too high.
I get a lot of error when try to compile the project
Error: Error opening /data/ts_farm/kentan/2019/October/Forum_rgmii/a.0/fpga/ip/qsys/nios_qsys/ip/nios_qsys/mutex_2_h2f_nios_0.ip.
Error: Error opening /data/ts_farm/kentan/2019/October/Forum_rgmii/a.0/fpga/ip/qsys/nios_qsys/ip/nios_qsys/nios_qsys_timer_0.ip.
Error: Error opening /data/ts_farm/kentan/2019/October/Forum_rgmii/a.0/fpga/ip/qsys/nios_qsys/ip/nios_qsys/mutex_3_to_h2f_bridge_0.ip.
Can you make sure that your ip directory zip down all the necessary files?
Thanks, I manage to run the full compilation on your design.
Did you follow the constrain provided in cv_soc_rgmii_5csxfc6.qar files? As I compare the sdc that you have written, there are some missing clock like the create_generated clock which is use of the switch.
Can you review your sdc again and match with the example above?