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gcohe5
Novice
491 Views

altera gmii to sgmii ip timing problem

hi,

i’m trying to run the a10_soc_devkit_sgmii (arria 10) project (https://rocketboards.org/foswiki/Documentation/GSRD181ReleaseNotes#Release_Contents 1) with some modifications.

I’m running into some timing issues that seem to be from the altera_gmii_to_sgmii ip. 

attached is a screenshot from the report and the project archive.

 

thanks

 

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8 Replies
KennyT_Intel
Moderator
168 Views

You can take a look in this design, rewrite the sdc according to this design and see if you can meet the timing. Let me know how it goes.

KennyT_Intel
Moderator
168 Views

You will also need to take a look at:

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pd...

page 183 although this is A10, It should be apply to all device.

 

Basically, it mention that you need a different IO standards if your frequencies running too high.

 

KennyT_Intel
Moderator
168 Views

any update?

EFroh
Beginner
168 Views

Hi,

Rewriting the SDC according to the cv_soc_rgmii_5csxfc6 design didn't help me.

I attached an archive of the project, can you please help me with this timing issue?

 

(The project qpf is under fpga/synth/evb3022_synth)

 

Thanks,

KennyT_Intel
Moderator
168 Views

I get a lot of error when try to compile the project

 

Error: Error opening /data/ts_farm/kentan/2019/October/Forum_rgmii/a.0/fpga/ip/qsys/nios_qsys/ip/nios_qsys/mutex_2_h2f_nios_0.ip. 

Error: Error opening /data/ts_farm/kentan/2019/October/Forum_rgmii/a.0/fpga/ip/qsys/nios_qsys/ip/nios_qsys/nios_qsys_timer_0.ip. 

Error: Error opening /data/ts_farm/kentan/2019/October/Forum_rgmii/a.0/fpga/ip/qsys/nios_qsys/ip/nios_qsys/mutex_3_to_h2f_bridge_0.ip. 

 

Can you make sure that your ip directory zip down all the necessary files?

EFroh
Beginner
168 Views

Hi,

I added some files. please try the attached ZIP:

Thanks,

KennyT_Intel
Moderator
168 Views

Thanks, I manage to run the full compilation on your design.

 

Did you follow the constrain provided in cv_soc_rgmii_5csxfc6.qar files? As I compare the sdc that you have written, there are some missing clock like the create_generated clock which is use of the switch.

 

Can you review your sdc again and match with the example above?

KennyT_Intel
Moderator
168 Views

any update?

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