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Honored Contributor I
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altlvds tx external pll cyclone V

Hello, 

 

I am having trouble using and simulating altlvds tx with an external pll. I have read appropriate documentation and I have used the cyclonev_pll_lvds_output between pll and altlvds tx. 

I have not been able to simulate my design so I decided to try the example 'top_rxtx_external_pll_cyclonev_vhdl.qar' provided by altera. 

 

My question is : how to simulate this design ? 

 

Here is what I have done :  

Open design 

Synthesis 

Open modelsim-altera from quartus 

Modelsim altera performs compilation and exit with this error :  

 

# top level modules:# lvds_tx_lvds_tx# vcom -93 -work work {c:/users/xxx/desktop/test_alt_2/top_rxtx_external_pll_cyclonev_vhdl_restored/top.vhd}# model technology modelsim altera vcom 10.1d compiler 2012.11 nov 2 2012# -- loading package standard# -- loading package textio# -- loading package std_logic_1164# -- compiling entity top# -- compiling architecture rtl of top# ** error: c:/users/xxx/desktop/test_alt_2/top_rxtx_external_pll_cyclonev_vhdl_restored/top.vhd(115): (vcom-1436) actual expression (infix expression) of formal "ccout" is not globally static.# # ** error: c:/users/xxx/desktop/test_alt_2/top_rxtx_external_pll_cyclonev_vhdl_restored/top.vhd(135): vhdl compiler exiting# ** error: c:/altera/13.0sp1/modelsim_ase/win32aloem/vcom failed.# error in macro ./top_run_msim_rtl_vhdl.do line 21# c:/altera/13.0sp1/modelsim_ase/win32aloem/vcom failed.# while executing# "vcom -93 -work work {c:/users/xxx/desktop/test_alt_2/top_rxtx_external_pll_cyclonev_vhdl_restored/top.vhd}" 

 

Changing this :  

lvds_clock_buffer_inst0 : cyclonev_pll_lvds_output 

generic map ( 

pll_loaden_enable_disable => "true", 

pll_lvdsclk_enable_disable => "true" 

port map (ccout => rxtx_enable & rxtx_inclock; 

loaden => buf_loaden, 

lvdsclk => buf_lvdsclk 

); 

 

into that :  

ccout <= rxtx_enable & rxtx_inclock; 

lvds_clock_buffer_inst0 : cyclonev_pll_lvds_output 

generic map ( 

pll_loaden_enable_disable => "true", 

pll_lvdsclk_enable_disable => "true" 

port map (ccout => ccout, 

loaden => buf_loaden, 

lvdsclk => buf_lvdsclk 

); 

 

makes the compilation work in ModelSim-altera. 

 

Then I create a basic testbench, compile it and simulate it. The next error is :  

# ** fatal: error occurred in protected context.# time: 0 ps iteration: 0 protected: /testbench/dut/pll_inst0/mypll_altera_pll_altera_pll_i_622/<protected>/<protected>/<protected> file: nofile# fatal error while loading design# error loading design 

 

Then re-compiling pll files. The next error is :  

** error: (vsim-3039) c:/users/xxx/desktop/test_alt_2/top_rxtx_external_pll_cyclonev_vhdl_restored/top.vhd(50): instantiation of 'mypll_0002' failed.# # region: /testbench/dut/pll_inst0# loading work.cyclonev_pll_lvds_output(behavior)# ** error: (vsim-3732) c:/users/xxx/desktop/test_alt_2/top_rxtx_external_pll_cyclonev_vhdl_restored/top.vhd(121): no default binding for component instance 'lvds_clock_buffer_inst0'.# # the following component ports are not on the entity:# reconfig_from_pll# reconfig_to_pll# locked# outclk_2# outclk_1# outclk_0# rst# refclk# # region: /testbench/dut/lvds_clock_buffer_inst0# ** warning: (vsim-3473) component instance "inst : cyclonev_pll_lvds_output_encrypted" is not bound.# time: 0 ps iteration: 0 instance: /testbench/dut/lvds_clock_buffer_inst0 file: c:/altera/13.0sp1/quartus/eda/sim_lib/cyclonev_atoms.vhd# error loading design 

 

I cannot go any further. Does someone know how to properly simulate this project ? 

 

 

Thank you very much. 

Matthieu
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