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In the user guide, it requires following for half rate write operation. (see my attached pic).
I found it cause some problem sometimes, it may write wrong data for next step.
But if I removed it, no issue for write. So what's the purpose of it, can we just jump to step 2
The following sequence corresponds with the numbered items in Figure 8–2:
1. The user logic asserts the first write request to row 0 so that row 0 is open before
the next transaction.
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Hello,
May I know about the issue that you are facing? Is it in simulation or actual hardware?
Are you able to provide some snapshots of the problem?
Regards,
Adzim
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It's actual hardware.
Let me describe issue:
step1) write data 512 bytes from address = 0
step2) write data 512 bytes from address = 512
............................
step3) finish write data of all ddr size.
step4) read data 512 bytes from address = 0
step5) read data 512 bytes from address = 512
............................
For expectation, all read data should be the same as write one.
but sometimes, the 1~2 bytes data of 512 bytes goes different if I done below action for write process.
1. The user logic asserts the first write request to row 0 so that row 0 is open before
the next transaction.
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Hello,
I was looking for the related issue with DDR2 write operation but does not see this specific issue yet.
But I think it's should be fine to jump to step 2 since it's working.
Regards,
Adzim
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As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
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