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altpcietb_tlbfm_rp location PCIe simulation

LastHorizon0711
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Hi there, 

 

I am doing some PCIe design and simulation. In the Intel generated example there is reference to a module named "altpcietb_tlbfm_rp" as part of the generated simulation files. I cannot find this module, does anyone know where it lives? and does anyone know what it does? from the port list it looks like I can specify a 1001 bit bus of user data to be injected over the PCIe interface.  

 

Many thanks 

Alex 

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skbeh
Employee
127 Views

Hi Sir

I looked into the Arria 10 PCIe AvMM User Guide, doesn't found the mention of 'altpcietb_tlbfm_rp'

May I know your generated example design is targeting which FPGA devices? Cyclone 10, Arria 10, Stratix 10 or Agilex?


Intel Arria 10 and Intel Cyclone 10 GX Avalon Memory Mapped (Avalon-MM) Interface for PCI Express User Guide

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf


In Chapter 13 of above user guide, there is a driver module called 'altpcietb_bfm_rp_gen3_x8.sv' 

Chapter 13 provided the testbench instantiates an endpoint design example and a Root Port BFM.

Probably this is what you are looking for.


Chapter 14 provided the simulation testbench that instantiates a Root Port design example of the Avalon-MM

Arria 10 Hard IP for PCIe and an Endpoint BFM.


You can follow the steps in these chapters to run the simulation.


LastHorizon0711
96 Views

Hi there, 

 

I am generating an example for Cyclone V GT devices; so this is a gen2x4 interface. (I would love to be using a more modern device - but don't have the funds!)  

 

The reference to this module may be found in the file: 

<root>\pcie_de_gen2_x4_ast64\testbench\pcie_de_gen2_x4_ast64_tb\simulation\submodules\altpcie_tbed_sv_hwtvl.v 

on line 303 

 

LastHorizon0711_0-1653910668853.png

Specifically, this module is instantiated when the design is not a root port.

 

Thanks 

Alex  

 

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