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Honored Contributor I
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alttemp_sense does not aplly the required clock divider

Hello everybody, 

 

I was using the alttemp_sense core on Stratix4 with pleasure up to now, but lately the clock divider that I have set is not applied, I have no idea what have changed. 

 

In the IP I have the following settings: 

--alttemp_sense CBX_AUTO_BLACKBOX="ALL" CLK_FREQUENCY="50.0" CLOCK_DIVIDER_ENABLE="on" CLOCK_DIVIDER_VALUE=80 DEVICE_FAMILY="Stratix IV" NUMBER_OF_SAMPLES=128 POI_CAL_TEMPERATURE=85 SIM_TSDCALO=0 USE_WYS="on" USER_OFFSET_ENABLE="off" clk tsdcaldone tsdcalo ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106 

--VERSION_BEGIN 11.1SP2 cbx_alttemp_sense 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_counter 2012:01:25:21:13:53:SJ cbx_lpm_decode 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_stratixiii 2012:01:25:21:13:53:SJ cbx_stratixv 2012:01:25:21:13:53:SJ VERSION_END 

 

 

As you see the clock divider is enabled and set to 80. 

 

In the fitter report I have: 

Info (332110): create_generated_clock -source {i_masterClkRstGen|i_mainPLL|altpll_component|auto_generated|pll1|clk[0]} -divide_by 40 -duty_cycle 50.00 -name {i_l0_sysregs|i_temp_sensor|temp_sensor_alttemp_sense_vps_component|sd1|clk} {i_l0_sysregs|i_temp_sensor|temp_sensor_alttemp_sense_vps_component|sd1|clk} 

 

==> which is a divider by 40.... it ends up giving me a much higher sampling rate, and the senor's ADC fail... 

 

Can someone tell me why the divider is not applied correctly ? 

 

thanks, 

Nico
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