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avalon-mm pipelined read completion order

Altera_Forum
Honored Contributor I
797 Views

Hi, 

 

I'm having a weird problem with a system that includes several custom Avalon-MM devices. In particular, there is a custom master that issues pipelined reads to two different slaves. One slave has a read latency of 2 cycles (onchip RAM with address and data registers), the other slave is a custom slave with variable read latency (readdatavalid is typically raised after 4 cycles). 

 

It seems that if pipelined reads are issued to both slaves at the same time, it is possible to get into a situation where both slaves are attempting to respond with valid read data on the same cycle. Consider: 

 

Slave A: read latency = 4 cyc 

Slave B: read latency = 2 cyc 

 

Cycle 1: Master issues read to slave A (0). 

Cycle 2: Master issues read to slave A (1). 

Cycle 3: Master issues read to slave B (0). 

Cycle 4: Master issues read to slave B (1). 

Cycle 5: Master issues read to slave B (2). readdatavalid from slave B (0). readdatavalid from slave A (0). 

 

On cycle 5, both slaves respond with readdatavalid. One of the responses gets lost since the system arbitration seems to pick one and ignore the other. 

 

To yield correct results the arbitration must return the valid readdata from slave A, since its request was issued first (Avalon-MM is supposed to be in-order). I would expect the readdata from slave B to be buffered and returned later, or wait states inserted by the arbitration layer preventing me from issuing potentially conflicting reads in the first place. But this is not what I see with signaltap, I end up losing some reads due to this overlap. If I count the number of cycles where the master's read=1 and waitrequest=0 versus the number of readdatavalid=1 cycles, they do NOT match, indicating that some reads simply disappeared. 

 

Is there any reference on what is supposed to happen in this case? Is this a bug in the generated Avalon-MM implementation? Am I doing something wrong?
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1 Reply
Altera_Forum
Honored Contributor I
53 Views

Replying to myself here because I found something interesting... 

 

It seems that this is a real issue with Avalon-MM. In fact, the code that generates the arbitration logic (quartus/sopc_builder/bin/europa/e_ptf_slave_arbitration_module.pm) has a routine to deal with this problem: sub _ensure_latent_master_reads_coherently at line 5850 in 9.1. However, this code only deals with fixed-latency slaves. The problem is that my system has one fixed and one variable-latency slave, so it is difficult to tell if two reads will complete correctly because you never know on what cycle the variable-latency slave will assert readdatavalid. Probably the cleanest fix would be for the arbiter to always assert waitrequest if a master attempts to switch slaves while reads are still outstanding to the variable-latency slave. 

 

I implemented a bridge component to do exactly this and it seems to fix the problem, but it is a total hack (relies on knowledge and careful design of memory map). I guess I will be contacting Altera directly.
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