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FPGA Intellectual Property

Discussions

TSE + Custom PCB w/Vitesse VSC8601

In 100G MAC+PHY simulation tx5l_ack signal sometimes goes to zero

Complex Coefficients with FIR Compiler II

Linux device driver for Altera PCI Express Chaining DMA reference design

10_100_1000 Mbps tri-mode ethernet MAC

how to add SGDMA RX/TX to the multiport tse mac?

stratix IV on DE4

PLL's error on ARRIA II GX

Simulation Alpha Blending Mixer IP core

64 bit DMA for memory to custom component only transfers 32 bit!

Stritix IV + DDR3 controller write unstable

DDR3 controller issue

Pin Assignment Error

SDRAM Memory Controller

SerDes GX module doesn't see the GX clocking signal

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Pin allocation for PCIe HIP gen 2 x1 with Avalon-MM Interface

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