FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

Simple custom 32x16bit register slave for Qsys Avalon MM interface

DDR and DDR2 SDRAM High-Performance Controller User Guide: question

Pcmcia

Stratix IV M9K blocks usage through DSP Builder

Does logarithm megafunction do well??

PCIe BFM

New IP development

How can i use the tse ip core with qsys?

MAC Address on altera de2 board

What is the polarity of DCLK signal in EPCS16 ?

Avalon Streaming Interface with FIR

Interfacing custom logic to SDRAM controller IP without using NIOS

How can i make the Marvel 88E1111 PHY chip work properly?

IPS-embedded suite contains DDR2 Altmemphy?

reference design with DDR3 DIMMs

Featured Content

Tone Mapping Operator IP Malfunctioning

Unable to simulate DDR3 controller

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)