FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

Floating Point atan Megafunction

Need FPGA application that can act as DDR3 dimm

Matrix inverse megafunction

PCIe EndPoint IP

Bandwidth Calculation of PCIe data Transfer for arria II speed -x1

SPI Core: Strange problem with sample and shift clocks

cacheable PCIe BAR

Issue with my FFT test "program"

NEEK VIP design example without NIOS II processor

PCI-E gen3 HIP simulation

FFT Megafunction problem - strange spikes

PIO Core initialization value and pin output

New Avalon OpenCores Ethernet MAC

compile issue with design unit generic_pll

Choosing TCP/UDP ip core (+ mac?), no SoC, anyone?

Featured Content

Pin allocation for PCIe HIP gen 2 x1 with Avalon-MM Interface

Platform Designer and DSP Builder

Intel P-tile Avalon ST BAR0 addr_offset

Re: Re:PCIe design reference recommendation (Cyclone 10 GX)