FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

mpeg encoder solution

Simple RNG for the DE2 board

What does this SOPC message mean?

error in compiling the RapidIO IP for Stratix II GX: EP2SGX90FF1508C3.

Scaler II vs Scaler problems

Overflow issue with building IIR filter using DSP builder basic block

FIR Compiler output is zero

DDR-SDRAM controler

HDL-master for SDRAM controller

Asynchronous/ controlling clock port of a flipflop

dsp builder-Prewitt edge detector

problems about 2D median filter

FFT Megacore in dsp builder

Dsp builder port number mismatches

question about ALTLVDS

Featured Content

Tone Mapping Operator IP Malfunctioning

Unable to simulate DDR3 controller

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)