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5954 Discussions

calibration of ddr4 interface on 10AX066H4F34E3SG

Andrey_Fazan
Novice
2,006 Views

Hello! I'm trying to implement DDR4 40bit-wide interface with 3 devices MT40A512M16LY-062E. When I connect only one of 3 devices to the project, calibration and data exchange do well, but when I connect all 3 devices - calibration fails. Why it happens and how can it be fixed?

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26 Replies
AdzimZM_Intel
Employee
1,709 Views

Hello sir,


I'm Adzim. Thanks for using Intel Community.


There are some possible causes that produce the calibration error.

But I need ask some questions first.


Have you tested all the 3 devices individually?

I mean connect one device to the project and tests it.

Repeat with another device.


Or the issue only happens when you trying to use 3 device all together?


Because of you are going to use multiple device, please check the following:

Do you enable the EMIF Debug Toolkit option?

Do you enable the address mirroring option?

There is a known issue when using the 10AX066 device.

You have to make sure that the reset is held for about 200ms after the initialization process.


Is that possible to know the calibration error?


Thanks,

Adzim



Andrey_Fazan
Novice
1,702 Views

Hello, mr. Adzim!
I have tested each device individually (only one device was connected to the project). Calibration was successful in this case. This issue happens when I try to use 3 devices all together. And what about your checklist:
1. EMIF Debug Toolkit is enabled
2. How can I enable address mirroring option? (I use Quartus Prime Pro 20.2.0)
3. And how can I make reset to be held about 200ms after initialization?

And here is calibration status:

; Calibration Status Per Group ;
+-------+--------+----------------------+
; Group ; Status ; Error Stage ;
+-------+--------+----------------------+
; 0 ; Pass ; N/A ;
; 1 ; Pass ; N/A ;
; 2 ; Fail ; Read Per-bit Deskew ;
; 3 ; Fail ; Write Per-bit Deskew ;
; 4 ; Fail ; Write Per-bit Deskew ;

AdzimZM_Intel
Employee
1,670 Views

Hi Andrey_Fazan,


Thank you for sharing the calibration error.


Is the calibration always failed at that stage?

Which memory that the calibration is failing?


Can you try to disable the address and command leveling calibration?

You can set it in the IP Parameter Editor, under the Diagnostics tab,

select the Skip address/command leveling calibration.

I'm referring to the KDB in the link below. It's looks like the error is related.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...


The address mirroring option is in hidden parameter and I can see that the default value is already been enabled in Quartus Prime Pro 20.2.


Regards,

Adzim


Andrey_Fazan
Novice
1,663 Views

Hi! I disabled address and command leveling calibration, it didn't help. I made reset signal to be held 200ms (after power on), it also didn't help. 


Is the calibration always failed at that stage? - Yes
Which memory that the calibration is failing? - What do you mean here?

 

I attach full report of calibration for better understanding

AdzimZM_Intel
Employee
1,634 Views

Hi Andrey_Fazan,


Thanks for sharing the report.

Are you also able to attached the calibration report for the one device testing?


From the report, it's can be seen that the calibration is stopped at DQS2.

Can you identify which device that has been used for that group?

Can you check the connection on that device?


Can you confirm that all connections on your design are connected correctly?


Or if possible, can you test it on different board?


Thanks,

Adzim


Andrey_Fazan
Novice
1,623 Views

Hi, Adzim!
I attach reports for each memory device

From these reports, you can see, that every separate device calibrates correctly, so, I suppose, there are connected correctly too.

In archive:

- bank C - the first device (DQS0)

- bank B - the second device (DQS1, DQS2)

- bank A - the third device (DQS3, DQS4)

Such names for devices are just used in our project

AdzimZM_Intel
Employee
1,617 Views

Hi Andrey_Fazan,


Thanks for sharing the calibration reports.

I can see it as you mention it previously.


If that thus matter if you change the group for your device?

such as:-

- bank C - the first device (DQS0, DQS1)

- bank B - the second device (DQS2, DQS3)

- bank A - the third device (DQS4)


If it always stops the calibration at DQS2, it could be the process has been interrupted by the reset signal.

Can check that the reset signal is not triggered during the calibration process?


Regards,

Adzim


Andrey_Fazan
Novice
1,607 Views

Hi, Adzim!

If that thus matter if you change the group for your device? It is impossible to change group for devices because only 8 DQ pins from device "Bank C" are connected to the FPGA

Can check that the reset signal is not triggered during the calibration process? - Reset signal is not triggered

I attach also configuration list for EMIF example, hope, it can help to solve the problem

Thank you!

AdzimZM_Intel
Employee
1,595 Views

Hi Andrey_Fazan,


Thanks for sharing the EMIF IP configuration.


When I looked at your configurations, I can see that the ECC is not enable.

If I'm not mistaken, the 40bit = 32bit +8bit ECC.

Why not you disable the x8 SDRAM component and use both x16 SDRAM components to make a 32bit-wide interface?


Thanks,

Adzim


Andrey_Fazan
Novice
1,543 Views

Hi Adzim,

Yes, our purpose is to use ddr4 40bit-wide interface with ECC, but ECC was disabled until successful calibration. Both enabling ECC and disabling x8 component didn't help, I attach these reports

AdzimZM_Intel
Employee
1,476 Views

Hi Andrey_Fazan,

 

Are you able to implement your design in different board?

 

AdzimZM_Intel
Employee
1,461 Views

Hi Andrey_Fazan,


Can you check the signal integrity of the board?

You can change the OCT value in the EMIF IP.


Can you also perform a simulation by changing the DQS group with other memory?

I mean here is like a memory A is connects to the Group 0 and 1.

Then connects it to the Group 2 and 3.


Regards,

Adzim


AdzimZM_Intel
Employee
1,348 Views

Hi Andrey_Fazan,

 

I hope you're doing well.

 

Do you still get the error when enable all memories on the board?

 

Regards,

Adzim

Andrey_Fazan
Novice
1,292 Views

Hi, Adzim,

I still have some problems with all memories, but it went better. What did I do:

- in dqs pins from 39 to 0 I set memory groups in this order: lower and upper A (device 3), upper and lower B (device 2), and lower C. (device 1) (why did I set upper and then lower A - in other case, I have only 3/5 dqs group calibrated)

- in IP parameters: MemIO tab -> memory IO settings subtab -> Output drive strength setting - 40 ohm and ODT Rtt nominal value - 48 Ohm
Now, I have these calibration results: 
+---------------------------------------+
; Calibration Status Per Group ;
+-------+--------+----------------------+
; Group ; Status ; Error Stage ;
+-------+--------+----------------------+
; 0 ; Pass ; N/A ;
; 1 ; Pass ; N/A ;
; 2 ; Pass ; N/A ;
; 3 ; Pass ; N/A ;
; 4 ; Fail ; Write Per-bit Deskew ;
+-------+--------+----------------------+
So, now I can work with 32bit memory without ECC, but it still not what I expected. Moreover, we are going to make board for other project with at least 64bit wide memory interface, so I still need to solve this problem. I attach report and configuration for current project

AdzimZM_Intel
Employee
1,215 Views

Hi Andrey,


Have you changed the device or board?

Because I notify that you used difference speedgrade in you EMIF IP.


I'm not understand on how do you configured the memory order.

Can you show the board design topology for the memory device connection?

Maybe you can draw a diagram for all groups.


For your new project, I think you should run the board simulation first to identify the optimum OCT value that your board can get.


Regards,

Adzim


Andrey_Fazan
Novice
1,184 Views

Hi, Adzim,
I can share the PCB document for Altium Designer, it could be more informative.
Short info:
 - FPGA is A9.DD1; 
 - sdram bank C is A12.D3 (first device along the CK track, as I mentioned before);
 - bank B - A12.D2, 
 - bank A - A12.D1;

At the moment banks are connected to emif in this order (it gives the best calibration results, 4/5):
dq pins of emif: [39===sdram_a[7...0], sdram_a[15...8], sdram_b[15...8], sdram_b[7...0], sdram_c===0].

So, the last dqs group (sdram_a[7...0], or dq_pin[39...32]) could not be calibrated with all devices together. When I swap sdram_a[7...0] and sdram_a[15...8], I have only 3/5 (I attach reports for each variation of order, see the first line to define it).

Thanks!

AdzimZM_Intel
Employee
1,175 Views

Hi Andrey,


Thanks for sharing those files.


It's seems like the sdram_a[7...0] is the only group that failed in the calibration

Even after you swapping the group with sdram_a[15...8].

The sdram_a[15...8] group can do the calibration but not for the sdram_a[7...0].


There is one thing that I notice in the calibration report which is the VREFIN setting for the sdram_a[7...0] group is slightly lower than other.

Maybe you can take a look on the voltage for this group when running the calibration.

Also make sure that there is no connectivity problem on board.


You can try to set the Memory I/O Settings as below.

 • Output drive strength setting = RZQ/7 (34 ohm)

 • Dynamic ODT (Rtt_ WR) value = Dynamic ODT off.

 • ODT Rtt nominal value = ODT Disable.

 • Rtt Park = RZQ /3 (80 Ohm)


Thanks,

Adzim


Andrey_Fazan
Novice
1,162 Views

Hi, Adzim
These settings didn't help

You can try to set the Memory I/O Settings as below.

 • Output drive strength setting = RZQ/7 (34 ohm)

 • Dynamic ODT (Rtt_ WR) value = Dynamic ODT off.

 • ODT Rtt nominal value = ODT Disable.

 • Rtt Park = RZQ /3 (80 Ohm)

 

AdzimZM_Intel
Employee
1,160 Views

Hi Andrey,


Can you create a 32-bit data configuration and used the sdram_a[7...0] as the last group?


Thanks


Andrey_Fazan
Novice
1,136 Views

Hi, Adzim

I created such interface. Both sdram_a[7...0] and sdram_a[15...8] can be calibrated with sdram_b and sdram_c. I also tried to create an interface with only sdram_a and sdram_b (without sdram_c). Calibration was not successful. I attach report for each situation (as always the order of connection is at the top of each document)

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