checksum_accelerator

[Altera_Forum]

An example of SOPC component build has been provided by ALTERA in -altera avalon checksum accelerator design example readme version 3.0. in this example the controller and checksum calculator component has clock_reset is the clock and clock_reset_reset is shown as reset. why it should be so ? can't it be clock and clock_reset ?

[Altera_Forum]

Historically clocks and resets were included as a single interface. With Qsys these are being separated out into clock and reset interfaces. So you are probably just seeing that occur. clock_reset_reset is the reset input and clock .... is the clock. This splitting is happening behind the scenes by the tools so that is why they have weird names.

[Altera_Forum]

Thanks for the information. But I am not using Qsys and further, I also see clk and reset being used in one of the modules i.e,. the readmaster module of the same example. I don't know why clk / reset and clock_reset/clock_reset_reset are used in the different modules of the same example on checksum accelerator hardware component.? Any clarifications on this ?

[Altera_Forum]

A screenshot would say a thousand words.

[Altera_Forum]

file:///C:/DOCUME%7E1/Owner/LOCALS%7E1/Temp/moz-screenshot.png file:///C:/DOCUME%7E1/Owner/LOCALS%7E1/Temp/moz-screenshot-1.png file:///C:/DOCUME%7E1/Owner/LOCALS%7E1/Temp/moz-screenshot-2.png Sure. The SOPC system schematic is attached. 

 Regards

[Altera_Forum]

SOPC Builder is just showing them the same way as they would appear in Qsys. Those are tcl based components that have a seperate clock and reset interface and it is just being displayed as two ports. It would take too much text to explain this but at the end of the day you don't need to worry about this...

[Altera_Forum]

OK - I think I got it. Thank you for the explanation. I appreciate it.