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Altera_Forum
Honored Contributor I
1,181 Views

connecting 32 bit data to 128 bit data with avalon

I think it maybe a silly problem but I can't get it work. I want to connect my master with 32 bit datawidth to a ddr controller with 128 datawidth using qsys. But when I simulate it in modelsim, it shows that waitrequest is always assigned by interconnect component, while ddr controller doesn't assign waitrequest. 

 

I set my master address unit as symbol(8 bit), with 4 width byteenable, my slave address unit as word, with 16 width byteenable. 

 

Can anyone help me?
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5 Replies
Altera_Forum
Honored Contributor I
61 Views

Hello, 

 

Have you tried to initiate any read or write operation? By default wait request from interconnect fabric will be high but when you initiate any read or write operation, it would go low. ( According to Avalon specification, read or write operation can be initiated even when wait request is high.) 

 

Cheers, 

Bhaumik
Altera_Forum
Honored Contributor I
61 Views

 

--- Quote Start ---  

Hello, 

 

Have you tried to initiate any read or write operation? By default wait request from interconnect fabric will be high but when you initiate any read or write operation, it would go low. ( According to Avalon specification, read or write operation can be initiated even when wait request is high.) 

 

Cheers, 

Bhaumik 

--- Quote End ---  

 

 

Thankyou for your advance. 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=13444&stc=1  

 

fifotest0 is my master and fifo20 is slave. 

The write request is asserted by master, but interconnection still asserts waitrequest. And my slave receives nothing, the write request is disasserted.
Altera_Forum
Honored Contributor I
61 Views

I've had similar issues with the Altera DDR3 controller getting stuck and never asking for data when connected to Avalon-MM interconnect fabric - they don't seem to like each other very much. 

 

I made the attached Qsys IP core which allows narrow masters to connect to wide slaves. It seems to do the trick for me at least, so might be worth a try. Just select the Qsys parameters for the module to ensure that the output interface sideband signals match the DDR signals so that no fabric is inserted between.
Altera_Forum
Honored Contributor I
61 Views

Your picture is way too small, but the master must continue holding the command on the bus until waitrequest is deasserted. How long are you waiting before giving up on the command? Is there anything else going on in your system? Have you tried generating the example design with the parameters you mention to see how it simulates before connecting up to your own master?

Altera_Forum
Honored Contributor I
61 Views

The memory controller is probably going to issue waitrequest for around 500us from T=0 to simulate the initialization and calibration cycle of the memory. I vaguely recall it will accept a few burst requests then have to backpressure due to it's command queue being full (can't issue the reads/writes if the memory isn't functional yet). 

 

I think that controller has simulation settings to minimize this period of time so I would double check what they are set to since you might be just not running your simulation long enough with the current settings.
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