FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5952 Discussions

control block and DSP Builder

Altera_Forum
Honored Contributor II
791 Views

Hi, 

I have many experience in FPGA and verilog coding for implementing DSP System. Now I want to increase my speed for implementing DSP Systems. can DSP Builder help me? How can i overcome controlling parts in the DSP Builder? for example, when I use FFT IP Core in the Quartus II, I have many control IO signals to use FFT as burst or many application. Is it possible to use IP Cores with control signals?  

Best Regards
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
86 Views

My Experience: 

As far as I know, configuration parameters are available in DSP Builder. The problem however is synthesis control. When you code HDL and your timing is not met, you can do many efforts in order to speed up your circuits. You may pipeline your code, register some internal wire, change your adder, etc. 

In DSP Builder all of these options are not simply available. You are still able to for example pipeline your IP Core (If it has this option as in divider for instance), but your options are a few. 

I have experienced this issue in another vendor tool and finally I was told by the tool that I have to export my project and perform some tasks outside DSP Builder which meant it has less power compared to the main flow. 

Afterwards, I do not use DSP builder, since all IP cores are also available in MegaWizard/IP Catalog. HDL coding may be prohibited, but this is not a difficult task for an experienced hardware designer. 

You are free when you design based on HDL.
Reply