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Altera_Forum
Honored Contributor I
1,218 Views

cyclone II ALTLVDS_RX ipcore issue?

i am using ALTLVDS_RX ipcore on cyclone II device, but meet a problem that rx parral datas are not correct. the following is the ipcore configration. any advice?  

 

 

ALTLVDS_RX_component.buffer_implementation = "RAM", 

ALTLVDS_RX_component.cds_mode = "UNUSED", 

ALTLVDS_RX_component.common_rx_tx_pll = "OFF", 

ALTLVDS_RX_component.data_align_rollover = 4, 

ALTLVDS_RX_component.data_rate = "519.75 Mbps", 

ALTLVDS_RX_component.deserialization_factor = 7, 

ALTLVDS_RX_component.dpa_initial_phase_value = 0, 

ALTLVDS_RX_component.dpll_lock_count = 0, 

ALTLVDS_RX_component.dpll_lock_window = 0, 

ALTLVDS_RX_component.enable_clock_pin_mode = "UNUSED", 

ALTLVDS_RX_component.enable_dpa_align_to_rising_edge_only = "OFF", 

ALTLVDS_RX_component.enable_dpa_calibration = "ON", 

ALTLVDS_RX_component.enable_dpa_fifo = "UNUSED", 

ALTLVDS_RX_component.enable_dpa_initial_phase_selection = "OFF", 

ALTLVDS_RX_component.enable_dpa_mode = "OFF", 

ALTLVDS_RX_component.enable_dpa_pll_calibration = "OFF", 

ALTLVDS_RX_component.enable_soft_cdr_mode = "OFF", 

ALTLVDS_RX_component.implement_in_les = "ON", 

ALTLVDS_RX_component.inclock_boost = 0, 

ALTLVDS_RX_component.inclock_data_alignment = "EDGE_ALIGNED", 

ALTLVDS_RX_component.inclock_period = 13468, 

ALTLVDS_RX_component.inclock_phase_shift = 1684, 

ALTLVDS_RX_component.input_data_rate = 519, 

ALTLVDS_RX_component.intended_device_family = "Cyclone II", 

ALTLVDS_RX_component.lose_lock_on_one_change = "UNUSED", 

ALTLVDS_RX_component.lpm_hint = "CBX_MODULE_PREFIX=lvds_rx", 

ALTLVDS_RX_component.lpm_type = "altlvds_rx", 

ALTLVDS_RX_component.number_of_channels = 8, 

ALTLVDS_RX_component.outclock_resource = "AUTO", 

ALTLVDS_RX_component.pll_operation_mode = "SOURCE_SYNCHRONOUS", 

ALTLVDS_RX_component.pll_self_reset_on_loss_lock = "UNUSED", 

ALTLVDS_RX_component.port_rx_channel_data_align = "PORT_UNUSED", 

ALTLVDS_RX_component.port_rx_data_align = "PORT_UNUSED", 

ALTLVDS_RX_component.refclk_frequency = "UNUSED", 

ALTLVDS_RX_component.registered_data_align_input = "UNUSED", 

ALTLVDS_RX_component.registered_output = "ON", 

ALTLVDS_RX_component.reset_fifo_at_first_lock = "UNUSED", 

ALTLVDS_RX_component.rx_align_data_reg = "UNUSED", 

ALTLVDS_RX_component.sim_dpa_is_negative_ppm_drift = "OFF", 

ALTLVDS_RX_component.sim_dpa_net_ppm_variation = 0, 

ALTLVDS_RX_component.sim_dpa_output_clock_phase_shift = 0, 

ALTLVDS_RX_component.use_coreclock_input = "OFF", 

ALTLVDS_RX_component.use_dpll_rawperror = "OFF", 

ALTLVDS_RX_component.use_external_pll = "OFF", 

ALTLVDS_RX_component.use_no_phase_shift = "OFF", 

ALTLVDS_RX_component.x_on_bitslip = "ON", 

ALTLVDS_RX_component.clk_src_is_pll = "off";
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6 Replies
Altera_Forum
Honored Contributor I
30 Views

i take two weeks on the issue, so it is urgent!!!!!!!!!!!!!!! please help.

Altera_Forum
Honored Contributor I
30 Views

If it is really urgent then you need to describe your problem better. What are you trying to achieve and what do you get instead? "rx parral datas are not correct" isn't really helping

Altera_Forum
Honored Contributor I
30 Views

 

--- Quote Start ---  

If it is really urgent then you need to describe your problem better. What are you trying to achieve and what do you get instead? "rx parral datas are not correct" isn't really helping 

--- Quote End ---  

 

 

 

ok, lvds data is from a RGB generater, i can control the RGB generater and generate any RGB data, for example all one , all zero, increment data. 

 

when i send increment data to lvds interface, altlvds_rx ip should recover 56bits increment data, but failed. some bits happen error.
Altera_Forum
Honored Contributor I
30 Views

Did you check the signal coming to the FPGA? How does the eye diagram look? 

How is the clock? Does the pll loose lock? 

Did you write timing constrains for your design and does the compile project meet timing requirements?
Altera_Forum
Honored Contributor I
30 Views

yes, i have checked all what you ask. timing constraint only include period constraint, what else? 

for the ip, i need constraint the location of FF registers?
Altera_Forum
Honored Contributor I
30 Views

Do you receive the clock on a separate pin? You need to specify the timing relationship between clock and data. Are you using a pll?