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Altera_Forum
Honored Contributor I
636 Views

cyclone iv15芯片接ddr2的问题

您好: 

我最近在做ddr2存储这方面的设计,fgpa芯片型号为 EP4CGX15,DDR2选用的是镁光科技的MT47H32M16CC芯片,由于fpga芯片管脚比较少,连接DDR2的BANK用到了BANK3-BANK7一共5个BANK,其中控制器的时钟为148.5MHz,fpga的上限频率为167MHz, 功能仿真已经实现,但是下到板子上却不能正常工作。以下具体列出我们遇到的问题: 

1,编译通过,但是存在时序警告,对设计做了时序约束后,问题还是存在。 

2,用10.0版本,10.1版本,11.0版本都定制过ip核,但是逻辑分析仪采不到数据,init_done始终为低。后来用9.1版本定制ip核,在10.0以上版本编译,逻辑分析仪能采到数据,并且 init_done为高,有读写操作,可是读出来的数据不对(读出来的一直为相同的一个或几个数),控制信号也没有数。 

现在想咨询下你们有没有在15系列上挂ddr2的成功案例。会不会是管脚分布太散,内部逻辑走线复杂导致时序无法满足还是其他原因,期待您的答复!
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7 Replies
Altera_Forum
Honored Contributor I
42 Views

If you post in english, you might get a better response.

Altera_Forum
Honored Contributor I
42 Views

你这个问题太专业,估计没人能回答你。我在CyclineIII上尝试设计过DDR2,由于管脚分配问题,没成功。 

init_d one 状态不确定,个人认为和版本没关系,应该是你的软件或者硬件设计的问题。极有可能是很小的一个软件程序错误。 

时序无法满足,可以降频试试。说实话,除了很简单的逻辑,频率稍微高点,我的设计时序很少能满足过,但都能用。 

频率高了,片内资源占用多了,quartus的fitting 每次都不一样,都有可能出错。我近来的设计就发现这个问题。因此,减少设计的资源占用再试试。
Altera_Forum
Honored Contributor I
42 Views

谢谢你的回复!我用的ddr2有最低频率限制的啊,手册上写的是125MHz,但是在定制的时候用到140以下的频率就会报错了,报错Trtp不能满足要求。软件应该不存在问题,因为软件部分的ip核和驱动都是自己生成了,也没改什么地方,硬件也仔细检查过了。你说你在三代上做的时候管脚分配错了,那应该编译不过吧。

Altera_Forum
Honored Contributor I
42 Views

谢谢你的回复!我用的ddr2有最低频率限制的啊,手册上写的是125MHz,但是在定制的时候用到140 以下的频率就会报错了,报错Trtp不能满足要求。软件应该不存在问题,因为软件部分的ip核和驱动都是自 己生成了,也没改什么地方,硬件也仔细检查过了。你说你在三代上做的时候管脚分配错了,那应该 编译不过吧。

Altera_Forum
Honored Contributor I
42 Views

ddr接fpga最好都接在同个bank上或相邻为好,你这种情况多半是时序,频率降低再试试看行不。quartus软件和ip核理论上讲是不会存在问题。

Altera_Forum
Honored Contributor I
42 Views

Please do not post the same question multiple times, you won't get more answers. Writing in English might work best though...

Altera_Forum
Honored Contributor I
42 Views

I used google translator: 

I recently did ddr2 memory in this design, fgpa chip model EP4CGX15, DDR2 choices are Micron Technology MT47H32M16CC chip, due to less fpga chip pin, connect to DDR2 BANK uses a total of five BANK3-BANK7 BANK, which controller clock is 148.5MHz, fpga maximum frequency of 167MHz, functional simulation has been achieved, but next to the board but does not work. We listed the following specific problems: 

1. Compile, but there are warning timing, timing constraints on the design done, the problem still exists. 

2. With 10.0, 10.1, 11.0 ip customized version of the nuclear, but not to adopt the logic analyzer data, init_d one is always low. Later, with the 9.1 version of the custom ip core, compiled in 5.0 above, the logic analyzer can be taken to the data, and init_done high, read and write operations, but not read out the data (the same has been read out of one or several number), not the number of control signals. 

Now want to consult your family have hung ddr2 in 15 successful cases. Distribution will not be too loose pin, the internal logic complexity resulting sequence alignment can not be met or for other reasons, look forward to your reply!" 

 

I was just curious what they were talking about. Cheers
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