FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

cyclone xcvr 10g phy

mengyaozhu
Beginner
783 Views

测试cyclone10  10G transerver phy ip时,10gbase-r 

 

求解:

 

 tx_parallel_data 信号,fb控制信号可以在64bit 任意byte位置上么 ,仿真时  只能在tx_control=01的

 字节位置上。

 

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ZiYing_Intel
Employee
705 Views

Hi,


Can share your .qar file here? So that I can try debug the issue from my side.


Best regards,

zying


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ZiYing_Intel
Employee
680 Views

Hi,


Can share your .qar file here? So that I can try debug the issue from my side.


Best regards,

zying


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ZiYing_Intel
Employee
656 Views

Hi,


For your information, the width of tx_parallel_data and tx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then tx_parallel_data = 64 bits and tx_control = 3 bits. The value 2'b01 indicates a data word and the value 2'b10 indicates a control word.


Best regards,

zying


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ZiYing_Intel
Employee
597 Views

Hi,


Since no hear any feedback from you, I am now close the case. If you have any question after the case closed, please do feel free to submit another issue.


Best regards,

zying


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