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Altera_Forum
Honored Contributor I
706 Views

ddr2 high-performance controller to slow?

hi @ all, 

in an traceunit i have implemented an self-built avalon master (memory mapped) which is connected to a ddr2 high-performance controller with hpcII and i connected them with the sopc-builder. the master gets 64-bit-wide data from a fifo with a frequency of 80mhz. the memory interface to the ddr2 ram ist 32 bit wide. 

in my simulation i saw, that the master writes only the 64-bit-wide words with an frequency of 16mhz to the controller because the sopc-builder creates a bridge to the ram-controller to use burst mode and this bridge drives the waitrequest signal. my master is not able to work in burst mode. unfortunately i can not change the speed when i change the value of "local maximum burst count" to 1 or 64 in the controller settings. 

is there any possibility to boost the data between my master and the ram-controller? 

it works with an sd-ram controller without any problems and i do not want to build a new master. 

what ist the problem here? 

it would be very nice to get helpful answers! 

regards 

steffen
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Altera_Forum
Honored Contributor I
30 Views

It sounds the SDRAM is being exposed as a x64 slave port with burst length of 2 to the fabric. If your master is non-bursting then that means you will at most be able to achieve 50% efficiency of the memory total bandwidth. I'm not sure how efficient the memory controller will be if you set the local burst count to 1 so maybe these steps would work best for you: 

 

1) Configure the memory controller for half rate operation (this will double the width of the local side to 128-bits, burst length of 1, and half the clock rate) 

 

2) Configure your master to operate on (non-bursting) 128-bit data 

 

3) If there are multiple masters competing for the memory, increase their arbitration shares so that multiple sequential accesses can get through
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