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Altera_Forum
Honored Contributor I
1,051 Views

ddr3 altmemphy problem

i use the mega altmemphy to produce a ddr3 controller,sim is ok,(200us mem_rst_n gets high,700us begin ini),but on board,i cannot get any result,how should i verify it? 

 

In signaltap ,mem_rst_n is always low,complete is low ,almost everyone is low,oh i'm going crazy...
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10 Replies
Altera_Forum
Honored Contributor I
51 Views

In Quartus: Tools -> External Memory Interface Toolkit. Wait for all JTAG connections to be discovered and wait for UniPHY to respond with the results. You'll see PLL status and controller status.

Altera_Forum
Honored Contributor I
51 Views

thank u ,i try

Altera_Forum
Honored Contributor I
51 Views

i use toolkit takes me this message: 

this releases of the debuggui does not match the veision of the altmemphy,.... and the result is an error,to cantact altera  

 

the version is which? my QII is 11.0,must i download 11.1?
Altera_Forum
Honored Contributor I
51 Views

the toolkit you mentioned is used for uinphy?i'm not sure,when i use it,message me no uniphy. I USE ALEMEMPHY,so i download a new toolkit named TOOLKIT_GUI,esp for altmemphy,So Mr Socrates(I just noticed your name,soooooory ),could U give me more Sugg?

Altera_Forum
Honored Contributor I
51 Views

Thank u again!!!!!!

Altera_Forum
Honored Contributor I
51 Views

The latest progress,the signal 'ctl_cal_fail' turns to hign in 806us after rst,means what ?

Altera_Forum
Honored Contributor I
51 Views

always @ the same times everytime

Altera_Forum
Honored Contributor I
51 Views

Read UniPHY User Guide. Check that signal. Anyway, I suppose the controller fails DDR3 calibration.

Altera_Forum
Honored Contributor I
51 Views

set location assignment PIN - xxx -to termination_blk0~ _rdn_pad 

set location assignment PIN - xxx -to termination_blk0~ _rup_pad 

 

final is ok,do u know why?
Altera_Forum
Honored Contributor I
51 Views

Yes, these resistors are dedicated for calibration purpose. Check schematics and again, READ USER GUIDE.

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