Is there any design example available which shows APB master & APB slave or AHB master & AHB slave interface in platform designer.
Edit component instantiation option where i can change the description of interface. So than it will also affect RTL code of that IP.
Please clarify these doubts
Only can find design example for AXI.
Refer to the attached file.
Documents and design resources links (search for keyword AXI):
https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/desig... (Intel® FPGA Design Examples)
Course training and video:
Is there any design example related to cypress superspeed EZ-USB FX3 connection with cyclone 10 gx intel fpga. The connection with cypress and cyclone 10 gx using interconnection board diagram.
Please help me to solve this issues.
Since there are no further feedback for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.