input spi_data_i;
output reg spi_data_o;
reg [15:0]shift_sender;
reg [15:0]shift_receiver;
code 1: spi receiving code=========================================================
always @(posedge spi_clk_50M or negedge spi_rst_n)
begin
if(~spi_rst_n)
shift_receiver <= 16'h0;
else
shift_receiver <= {shift_receiver[14:0],spi_data_i};
end
code2 :spi sending code ============================================================
always @(posedge spi_clk_50M or negedge spi_rst_n)
begin
if(~spi_rst_n)
begin
shift_sender <= 16'h0;
spi_data_o <= 1'b0;
end
else
begin
spi_data_o <= shift_sender[15];
shift_sender <= {shift_sender[14:0],1'b0};
end
end
============================
I am implemented a spi interface which clock is 50Mhz shown above, the sending code work correctly,but the receiving code can not receive any data using verilog to implement the shifting in register?
I have implemented a uart interface which clock fequency is 1Mhz using the simliar code above,the receiver and sender all work correctly;
do the LPM_SHIFTREG must be used in the serical receiving code when the clock fequency is too fast such as 50Mhz?why ?
