just like Figure 5. Architecture of 2.5G, 1G/2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/10G (MGBASE-T) Configuration
in document 1/2.5/100G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
The reference design can be generated insides low latency 10G MAC IP directly. The reference design will contains both MAC + PHY IP together.
You can also refer to below design example doc as reference.
The reference design is mostly build up based on Multirate PHY IP. It may switch more than just 1G <=> 10G.
For example, you can refer to chapter 3 (page 22) or chapter 5 (page 43) reference design.