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what we need is the MAC+PHY whole ref design
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10GE(1GE/10GE MAC) and 1GE/10GE multi-rate ethernet phy example design
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just like Figure 5. Architecture of 2.5G, 1G/2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/10G (MGBASE-T) Configuration
in document 1/2.5/100G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
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HI,
The reference design can be generated insides low latency 10G MAC IP directly. The reference design will contains both MAC + PHY IP together.
You can also refer to below design example doc as reference.
Thanks.
Regards,
dlim
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HI,
The reference design is mostly build up based on Multirate PHY IP. It may switch more than just 1G <=> 10G.
For example, you can refer to chapter 3 (page 22) or chapter 5 (page 43) reference design.
Thanks.
Regards,
dlim
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HI,
I hope I have clarified your doubt.
For now, I am setting this case to closure.
Thanks.
Regards,
dlim

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