Hi All,I downloaded the PCIe demo PCIe_DDR2_ref_dgn_arria2gx.qar; it seems to work well and the documentation is quite good. However, when I try to run the testbench in altpcietb_bfm_driver_chaining.v, it seems to get stuck in ebfm_barrd_wait. Basically, it sits waiting for an acknowledgement from the DDR memory, which doesn't seem to come back. I'm just running the testbench out of the box, in Altera's modelsim. Any thoughts on this? I can give more specific info if you think you can help.
Hi Again,I think I know what's going on now, it appears that in the simulation it takes about 300us to initialize RAM, through the DDR2 controller; but the simulation testbench assumed only a 300ns time. Is there anyway to modify the simulation DDR2 controller or set some global defines to speed up the DDR2 initialization process? I have read through some Altera documents that you should be able to, but I'm not sure how to set it up directly in my design.