editing hbm2 example design and simulating the new design.

[rsing93]

I m trying to understand hbm2 interfacing on stratix 10 using the example design generated using the ip programmer. I want to change some filss inside the example design and simulate the results to understand it better but i am not able to simulate the new design. Can i even change these files and if yes then how can i compile the modified design and simulate it.

Also, i am using modelsim for simulation and i am quite new to quartus so a more detailed answer will be very helpful.

[NurAida_A_Intel]

Hi Sir,

Thank you for joining this Intel Community.

HBM2 is integrated into Intel FPGA Stratix 10 MX devices using System In Package (SiP) technology. Devices include either 1 or 2 HBM2 stacks at the top and bottom of the package, and each stack is either 4 high or 8 high. Each HBM2 connected to an EMIB interface has a dedicated hard controller that can be customized for each physical channel. The controllers are connected to a Universal Interface Bus, or UIB, to access the EMIB to the memory. You may refer to this HBM2 UG for more details :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20031.pdf

Feel free to check out this online training for an overview of the HBM architecture and implementation:

https://www.intel.com/content/www/us/en/programmable/support/training/course/ohbms10.html

Upon completing this course, we recommend the following two follow-on courses:

• High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices: HBMC Features
• High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices: Implementation

Regarding the example design, may I know what kind of changes made and which file are you referring to?

Thanks

Regards,

Aida

[rsing93]

Thank you for your reply.

I have registered for the access to the courses stated and will go through them.

Also, the files I am changing belong to traffic generator IP. I am basically changing the LSFR implementation file to generate data of my choice rather than random data.

[NurAida_A_Intel]

Hi Sir,

Thank you for the explanation. Appreciated it. 😊

As I understand it, you are trying to change the traffic pattern and referring to this file --> XX_emif_avl_tg_lsfr ( please correct me if I'm wrong ).

Yes, you are able to change this LSFR traffic pattern for testing purpose. You need to create the specific control pattern that required and replace the file in the directory which your LSFR file located.

For additional information on changing the test duration and traffic pattern for the Intel Stratix 10 HBM2 traffic generator, refer to the Intel Stratix 10 High Bandwidth Memory (HBM2) Traffic Generator video, available here: https:// www.youtube.com/watch?v=XLfw12VCm0U.

It help user understand on how to change the test length as well and traffic pattern on the traffic generator for example design. At the end of the video, it demonstrate the simulation results on the changes done on the test length and traffic pattern.

I sincerely hope this helps.

Thanks

Regards,

Aida

[rsing93]

Hi,

I am not able to figure out how to create new simulation and synthesis ip files after changing the LSFR file. Every time I regenerate IPs using the IP regeneration process during compilation all the files are reset to their original form. The new IPs generated do not have the changes I made. The video mentioned by you in your reply does not go clarify that process.

[NurAida_A_Intel]

Hi Sir,

By right, user shouldn't re-generate IP again, user is expected to modify design and compile design only. Once user re-generate IP, everything will be reset to default setting in IP.

Regards,

Aida