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fail to access DDR2 SDRAM with Stratix III EP3SL340F1517I3

Altera_Forum
Honored Contributor II
861 Views

We are trying to implement a DDR2 controller example in an FPGA board designed by ourselves. The function simulation with the DDR2 controller IP is good in the modelsim. But after generating it in the quartus II 9.1 and downloading that into the board, something strange happened: 

 

during the DDR2 initial process, the current of power pin bursted up to 5A from 200mA, and the power dropped from 1.8V to 0.8V. Waiting for a long time(6~7s), local_init_done came active and the power recovered to 1.8V again. But after initialization, the controller could never write the DDR2 successfully, i.e., there is no signal when we probe the pin, which means no signal from FPGA.  

 

Could someone help to analyse and fix the problem, please?  

 

Thanks, 

 

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2 Replies
Altera_Forum
Honored Contributor II
94 Views

Could you have some unused pins connected to ground on the board, that have been set as outputs driving high in Quartus? (or the other way round)

Altera_Forum
Honored Contributor II
94 Views

Yeah, unused pins are connected to ground on the board, and they are set to input or tristate.

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