for intel fpga, avalon interconnect ip (equivalent axi interconnect ip in XILINX VIVADO)

[terry123]

Hi,

i was old user in xilinx fpga.

recently, i am studying intel fpga and i will use intel fpga.

what ip can be used for avalon interface interconnect ip which i can set number of master and agent by myself same as axi interconnect ip in vivado?

not only in platform designer but also in hdl code, i want to make interconnect ip for connecting many avalon master and agent channels using master and agent.

for example,  multiple avalon master(m0,m1,m2 ...) can access agent of one emif ddr4 ip by interconnect ip. or multiple avalon master(m0,m1,m2 ...) can access the agent of emif ddr4 ip, the agent of other ip by discriminating avalon address map.

[ShengN_Intel · Accepted solution]

Hi Terry,

Check this https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/How-to-connect2-Avalon-MM-masters-to-1-MM-slave/m-p/639952. I think don't have that particular IP like axi interconnect ip. Can directly connect those multiple avalon master to slave.

Yes, in Platform Designer (Qsys) you simply connect both masters to the same slave interface of the IP. You can do this in the Connections panel of the System Contents tab (clicking the correct dots) or select the slave interface there and open the Connections tab from the View menu and use the checkboxes there.

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

[ShengN_Intel]

Any further updates or considerations?