fundamental question about Jesd204b II

[dsun01]

Dear Intel Support/Expert, 

I created a Jesd204b IP with the following parameters. 

in main page, Device Family: Arria10, "both base and phy", "Receiver", subclass "1", Data rate" 6144Mbps. "enable soft PCS", "153.6MHz".

In the configurations page.

L=4, M = 16, enable Manual F configuration. 

F = 8, N= 16, N'= 16, S = 1, K = 20

[skbeh]

Hi David

The width of jesd204_rx_link_data[] is derived from formula jesd204_rx_link_data[(L*32)-1:0], it means each lane Max support 32-bit data (per frame).

Number of lanes per converter device (L value) is valid between 1-8.

To achieve width of 256-bit, it looks like you should configure the core to LMF=8,8,8, or LMF=8,16,8

then jesd204_rx_link_data[(L*32)-1:0] will becomes 256-bit.

[dsun01]

Hi Skbeh, 

That is the limitation of my application. I have total 16 lanes used for 4 AFE58JD48s, each AFE58JD48 only assigned 4 lanes. this is the reason that in another question I asked in the thread 

Fundamental question about Jesd204B, Lanes VS ADCs - Intel Communities

you told me the solution is possible to set the receiver in X40 LMF = 4X16X4, to decode transmitter in X80 LMF = 4X16X8(each frame 8 octets), the trick is to separate one 8 octets frame to 2 frame of 4 octets in the Intel Jesd204b IP. I am working on the simulation to verify it. this is the first time I use Jesd204B IP, so it will take me several weeks to fully understand it. if you have someone user set this way before or any application note besides AN833(AN833 is using two lanes to double the throughput, I think it is not same as what I am trying to achieve), that will be very helpful. 

Best Regards,

David

[skbeh · Accepted solution]

Hi Havid

The timing reference clock for the JESD204B IP core (txlink_clk, rxlink_clk) runs at data rate/40 because the IP core operates in a 32-bit data bus architecture after 8B/10B encoding.

So far I have not seen the use case of data rate/80.

[dsun01]

thank you very much.