06-09-2011 02:38 AM
I use the DDR2 SDRAM Controller v9.1(not the high performance) and my memory is MT47H32M16cc-3. The parameters are set as follows:clock speed 150MHz Data bus width 16bit local width 32bit Row 13bit Column 10bit Bank 3bit CL 5 the DDR2 works correctly when I use the example driver which is generated by IP, but it works incorrectly sometimes when I replace the example driver by my own driver. My driver is very simple, just writes some data into ddr2, then reads back. But I compare the read back data with the write data, sometimes they are different. And I also find if I just write less then six data at once, there will be no errors. When I write more than six data, there will be errors sometimes. The attached files contain the SignalTap file and my own driver file. Does anyone can tell me where I am wrong? Thanks a lot.
06-10-2011 07:40 AM
Hi,What FPGA are you compiling for? In the v10.1 controller there is a TCL script you have to run to make the appropriate IO and timing settings, did you run something like this? Maybe it's related to the following issue: http://www.altera.com/support/kdb/solutions/rd12132010_638.html You're zip file seems to be empty, if you post the files I can take a look at them.. Grtz, Olaf
06-10-2011 07:57 AM
--- Quote Start --- Hi, What FPGA are you compiling for? In the v10.1 controller there is a TCL script you have to run to make the appropriate IO and timing settings, did you run something like this You're zip file seems to be empty, if you post the files I can take a look at them.. Grtz, Olaf --- Quote End --- thank you very much for your help. My FPGA is StratixII EP2S90F1020C3. I don't run any tcl for the project actually, I will try your suggestion. The attached file just contains one SignalTap file and one design file, not the whole project. I will change it. Thanks again.